Firestorm: FRECPX (scalar, H) measurements

Code:

  frecpx h0, h0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	0	61	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038
1004	3037	23	0	12	61	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->2

Code:

  frecpx h0, h0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	61	19900	25	10100	100	10000	100	10000	500	1067451	0	30018	30037	30037	28588	0	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	29919	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	19900	25	10100	100	10000	100	10000	500	1067451	0	30018	30037	30037	28588	0	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	18	710	1	16	1	1	29919	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	19900	25	10100	100	10000	100	10000	500	1067451	0	30018	30037	30037	28588	0	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	29919	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	19900	25	10100	100	10000	100	10000	500	1067451	0	30018	30037	30037	28588	0	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	29919	0	10000	100	30038	30260	30038	30038	30038
10204	30037	225	0	61	19900	25	10100	100	10000	100	10000	500	1067612	0	30018	30037	30037	28588	3	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	29919	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	66	19900	25	10100	100	10000	100	10000	500	1067451	0	30018	30037	30037	28588	0	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	29919	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	162	61	19900	25	10100	100	10000	100	10000	500	1067451	0	30018	30037	30037	28588	0	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	3	710	1	16	1	1	29919	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	19900	25	10100	100	10000	100	10000	500	1067451	0	30018	30037	30037	28588	0	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	29919	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	19900	25	10100	100	10000	100	10000	500	1067451	0	30018	30037	30037	28588	0	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	29919	0	10000	100	30084	30086	30038	30038	30038
10204	30037	225	0	61	19900	25	10100	100	10000	100	10000	500	1067451	0	30018	30037	30037	28588	0	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	29919	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	0	0	0	61	19900	25	10010	10	10000	10	10000	50	1067451	0	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29919	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	61	19900	25	10010	10	10000	10	10000	50	1067451	0	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29919	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	61	19900	25	10010	10	10000	10	10000	50	1067451	0	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29919	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	61	19900	25	10010	10	10000	10	10000	50	1067451	1	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	30134	2	10000	10	30318	30323	30323	30227	30323
10024	30321	227	1	0	1	6	7	945	616	0	2084	19804	150	10018	11	10056	15	10252	66	1068578	0	30234	30369	30321	28735	29	28945	10263	20	10343	20	10402	30074	30367	6	1	10021	10	9	10	10	10000	10	2	0	1	0	7108	0	739	2	73	4	5	30173	3	10000	10	30323	30274	30368	30405	30322
10024	30358	227	1	1	0	6	6	927	616	1	2678	19804	138	10029	13	10056	10	10294	50	1068417	0	30270	30319	30319	28734	34	28956	10317	20	10343	22	10396	30419	30131	8	1	10021	10	9	10	10	10000	10	0	0	1	2	8170	0	740	3	72	3	2	30170	4	10000	10	30369	30370	30415	30373	30320
10024	30370	228	0	1	1	7	8	936	704	0	61	19900	25	10010	10	10000	10	10000	50	1067451	1	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29919	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	61	19900	25	10010	10	10000	10	10000	50	1067451	0	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	1	640	2	16	2	2	29919	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	61	19900	25	10010	10	10000	10	10000	50	1067451	1	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29919	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	61	19900	25	10010	10	10000	10	10000	50	1067451	1	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29919	0	10000	10	30086	30038	30038	30038	30038

Test 3: throughput

Count: 8

Code:

  frecpx h0, h8
  frecpx h1, h8
  frecpx h2, h8
  frecpx h3, h8
  frecpx h4, h8
  frecpx h5, h8
  frecpx h6, h8
  frecpx h7, h8

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80039	599	0	0	39	25	80100	100	80000	100	80000	500	640000	0	80020	80039	80039	69971	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	1	39	1	1	1	5117	0	16	0	0	80036	80000	100	80040	80040	80040	80040	80040
80204	80039	599	0	0	704	25	80100	100	80000	100	80000	500	640000	1	80020	80039	80039	69971	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5117	0	16	0	0	80036	80000	100	80040	80040	80040	80040	80040
80204	80039	600	0	0	704	25	80100	100	80000	100	80000	500	640000	1	80020	80039	80039	69971	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5117	0	16	0	0	80036	80000	100	80040	80040	80040	80040	80040
80204	80039	600	0	0	229	25	80100	100	80000	100	80000	500	640000	1	80020	80039	80039	69971	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5117	0	16	0	0	80036	80000	100	80040	80040	80040	80040	80040
80204	80039	599	0	0	39	25	80100	100	80000	100	80000	500	640000	1	80020	80039	80039	69971	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5117	0	16	0	0	80036	80000	100	80040	80040	80040	80040	80040
80204	80039	600	0	0	39	43	80100	100	80000	100	80000	500	640000	1	80020	80039	80039	69971	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5117	0	16	0	0	80036	80000	100	80040	80040	80040	80040	80040
80204	80039	599	0	0	39	25	80100	100	80000	100	80000	500	640000	0	80020	80039	80039	69971	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5117	0	16	0	0	80036	80000	100	80040	80040	80040	80040	80040
80204	80039	600	0	0	39	25	80100	100	80000	100	80000	500	640000	0	80020	80039	80039	69971	6	69993	80135	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5117	0	16	0	0	80036	80000	100	80040	80040	80040	80040	80040
80204	80039	600	0	0	39	25	80100	100	80000	100	80000	500	640000	0	80020	80039	80039	69996	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5117	0	16	0	0	80036	80000	100	80040	80040	80040	80040	80040
80204	80039	599	0	0	39	25	80100	100	80000	100	80000	500	640000	0	80020	80039	80039	69971	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5117	0	16	0	0	80036	80000	100	80040	80040	80040	80040	80040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	80039	599	0	1	0	0	0	0	0	50	25	80010	10	80000	10	80000	50	640000	1	80020	80039	80039	69986	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	19	16	20	13	80034	80000	10	80040	80040	80040	80040	80040
80024	80039	599	0	0	0	0	0	0	0	50	25	80010	10	80000	10	80000	50	640000	1	80020	80039	80039	69986	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	12	16	22	17	80187	80000	10	80040	80040	80040	80040	80040
80024	80039	600	0	0	0	0	0	0	0	50	25	80010	10	80000	10	80000	50	640000	1	80020	80039	80039	69986	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	14	16	26	12	80034	80000	10	80040	80040	80040	80040	80040
80024	80039	600	0	0	0	0	0	0	0	50	25	80010	10	80000	10	80000	50	640000	1	80020	80039	80039	69986	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	13	16	24	12	80034	80000	10	80040	80040	80040	80040	80040
80024	80039	600	0	0	0	0	0	0	0	50	25	80010	10	80000	10	80000	50	640000	1	80020	80039	80039	69986	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	13	16	21	15	80034	80000	10	80040	80040	80040	80040	80040
80024	80039	600	0	0	0	0	0	0	0	50	25	80010	10	80000	10	80000	50	640000	1	80020	80039	80039	69986	3	70019	80010	20	80000	20	80000	80088	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	12	16	17	16	80034	80000	10	80040	80040	80040	80040	80040
80024	80039	600	0	0	0	0	0	0	0	50	25	80010	10	80000	10	80000	50	640000	1	80020	80039	80039	69986	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	13	16	27	18	80111	80000	10	80040	80040	80040	80040	80040
80024	80039	600	0	0	0	0	0	0	0	71	25	80010	10	80000	10	80000	50	640000	1	80020	80039	80039	69986	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	12	16	20	16	80034	80000	10	80040	80040	80040	80040	80040
80024	80039	600	0	0	0	0	0	0	0	50	25	80010	10	80000	10	80000	50	640000	1	80020	80039	80039	69986	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	12	16	19	17	80034	80000	10	80040	80040	80040	80040	80040
80024	80039	599	0	0	0	0	0	0	0	50	25	80010	10	80000	10	80000	50	640000	1	80020	80039	80039	69986	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	1	5020	10	16	25	14	80034	80000	10	80040	80040	80040	80040	80040

FRECPX (scalar, H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations