Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRINT32X (vector, 4S)

Test 1: uops

Code:

  frint32x v0.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110001073116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723661254725100010001000398160130183037303724143289510001000100030373037111001100029073116112629100030383038303830383038
100430372396125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110001616273116112629100030383038303830383038
100430372406125472510001000100039816003018303730372414328951000100010003037303711100110001073116112629100030383038303830383038
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000373116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  frint32x v0.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372320000612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000071021611296330100001003003830038300383003830038
10204300372330000612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000000071011611296330100001003003830038300383003830038
10204300372330000612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000071011611296330100001003003830038300383003830038
10204300372330000612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000071011611296330100001003003830038300383003830038
10204300372330000612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000000071011611296330100001003003830038300383003830038
10204300372330000612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000000071011611296330100001003003830038300383003830038
10204300372330000612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000071011611296330100001003003830038300383003830038
10204300372330000612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000071011611296330100001003003830038300383013630038
10204300372320000612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000071011611296330100001003003830038300383003830038
10204300372330000612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037233000000006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100002006401232229629010000103003830038300383003830038
1002430037233000000006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000006402162229629010000103003830228300383003830038
1002430037233000000006129547251001010100001010000504277160030018300373003728286328767100102010000221000030037300371110021109101010000100000006402162229629010000103003830038300383003830038
1002430037233000000006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000006402162229629010000103003830038300383003830038
1002430037233000000006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000006402162229629010000103003830038300383003830038
10024300372320000000011729547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000006402162229629010000103003830038300383003830038
1002430037233000000008929547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000006402162229629010000103018030038300383003830038
1002430037233000000006129547251001011100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000006402162229629010000103003830038300383003830038
1002430037233000000006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000006402162229629010000103003830038300383003830038
1002430037233000000006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000306402162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  frint32x v0.4s, v8.4s
  frint32x v1.4s, v8.4s
  frint32x v2.4s, v8.4s
  frint32x v3.4s, v8.4s
  frint32x v4.4s, v8.4s
  frint32x v5.4s, v8.4s
  frint32x v6.4s, v8.4s
  frint32x v7.4s, v8.4s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)0318191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200691550003025801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000011151180160020036800001002004020040200402004020040
80204200391560003025801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000011151180160020036800001002004020040200402004020040
80204200391560003025801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000011151181160020036800001002004020040200402004020040
8020420039155004689125801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000011151180160020036800001002004020040200402004020040
80204200391560003025801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000011151180160020202800001002004020040200402004020040
80204200391560006426801161008001610080028500640196020029200492004999760999868012820080038200800382004820049118020110099100100800001000022251291232120046800001002004920049200492004920049
80204200481550006426801161008001610080028500640196120029200492004899760999868012820080038200800382004820048118020110099100100800001000022251291231120045800001002005020049200492004920049
802042004815600064268011610080016100800285006401960200292004820048997601099868012820080038200800382004820049118020110099100100800001000022251281231120045800001002004920049200492005020049
802042004815500064268011610080016100800285006401961200292004920048997601099868012820080038200800382004920048118020110099100100800001000322251291231120046800001002005020049200492004920049
802042004815500064268011610080016100800285006401960200292004920048997601099868021620080038200800382004820048118020110099100100800001000322251281231120045800001002005020049200492004920050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)dbddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039156104652580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100350202616025252003680000102004020040200402004020040
8002420039156001302580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100050202516020232003680000102004020040200402004020040
800242003915500402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100050202616028272003680000102004020040200402004020040
8002420039155001472580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100050201516012232003680000102004020040200402004020040
8002420039155001726080010108009810800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100050202716014272003680000102004020040200402004020040
800242003915600402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100050202616025272003680000102004020040200402004020040
800242003915600462580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100350201416026132003680000102004020040200402004020040
8002420039155015402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100350202516015252003680000102004020040200402004020040
80024200391550613612580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100050202616028212003680000102004020040200402004020040
8002420039155001762580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100050201316028272003680000102004020040200402004020040