Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRINT32Z (scalar, D)

Test 1: uops

Code:

  frint32z d0, d0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303724000000612547251000100010003981601301830373037241432895100010001000303730371110011000000000001040231222761100030383131308530383158
1004313324001226401772538431008101611504008641309030853084242111292612881387133130373132211001100000001243050880233222712100031343038315130383085
10043131240112264176835253843100810001300400864130903157308424316293213001210116131203132211001100000200228630790232222674100030853132308530853134
100431312410201441767452529251016100810003995121301830853133243212291010001242116131303084311001100000002028480950232222700100031693074312030743133
100431322410122648861254725100010001000398160030183037303724143289510001000100030373037111001100000000000730216222629100030383038303830383038
1004303723000012061254725100010001000398160030183037303724143289510001000100030373037111001100000010258650940224222696100030853038308631223122
1004308523000227617621472529421024100813003981600309031323168242012294510321162116231313167311001100000000028400940245222701100031333074307431333085
1004307324011326488572253825100810081150399512130183084313324148291410641322133031213085311001100004020030250940224222658100030383038308630863038
1004308424101114488867253843100810081150399512030543084308524147291410751162116130833085211001100000000230102940216222664100030853086308630853086
100430732411111328882253844100810081150399512030543085308524147291511501161100030373037111001100000000000730216222629100030383038303830383038

Test 2: Latency 1->2

Code:

  frint32z d0, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd2d5map dispatch bubble (d6)ddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003723306129547251010010010000100100005004277160030018300373003728271728740101002001000820010008300373003711102011009910010010000100001739001600296460100001003003830038300383003830038
102043003723306129547251010010010000100100005004277160130018300373003728271628740101002001000820010008300373003711102011009910010010000100000710011611296330100001003003830038300383003830038
102043003723306129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000710011611296330100001003003830038300383003830038
102043003723208929547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000710011611296330100001003003830038300383003830038
102043003723306129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000710011611296330100001003003830038300383003830038
102043003723206129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000710011611296333100001003003830038300383003830038
1020430037233072629547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000710011611296330100001003003830038300383003830038
102043003723306129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000710011611296330100001003003830038300383003830038
102043003723306129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373008411102011009910010010000100000710011611296330100001003003830038300723003830038
102043003723206129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000710011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
100243003722500612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
100243003722500612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229695010000103003830038300383003830038
100243003722500612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
1002430037224006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100030006402162229629010000103003830038300383003830038
100243003722500612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
100243003722500612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
100243003722500612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000006403162229629010000103003830038300383003830038
100243003722500612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
100243003722500612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  frint32z d0, d8
  frint32z d1, d8
  frint32z d2, d8
  frint32z d3, d8
  frint32z d4, d8
  frint32z d5, d8
  frint32z d6, d8
  frint32z d7, d8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042006115500003025801081008000810080020500640132200200200392003999776999080120200800322008003220039200391180201100991001008000010000111511801620036800001002004020040200402004020040
802042003915500003025801081008000810080020500640132200200200392003999776999080120200800322008003220039200391180201100991001008000010000111511801620036800001002004020040200402004020040
802042003915500003025801081008000810080020500640132200200200392003999776999080120200800322008003220039200391180201100991001008000010000111511801620036800001002004020040200402004020040
80204200391610010803025801081008000810080020500640132200200200392003999776999080120200800322008003220039200391180201100991001008000010000111511801620036800001002004020040200402004020040
802042003915500003025801081008000810080020500640132200200200392003999776999080120200800322008003220039200391180201100991001008000010000111511801620036800001002004020040200402004020040
802042003915500003025801081008000810080020500640132200200200392003999776999080120200800322008003220039200391180201100991001008000010000111511801620036800001002004020040200402004020040
8020920039155002703025801081008000810080020500640132200200200392003999776999080120200800322008003220039200391180201100991001008000010020111511801620036800001002004020040200402004020040
802042003915500003025801081008000810080020500640132200200200392003999776999080120200800322008003220039200391180201100991001008000010000111511801620036800001002004020040200402004020040
802042003915500003025801081008000810080020500640132200203200392003999776999080120200800322008003220039200391180201100991001008000010000111511801620036800001002004020040200402004020040
8020420039161000050525801081008000810080020500640132200200200392003999776999080120200800322008003220039200391180201100991001008000010000111511801620036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accdcfd2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9daddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420051155150402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100100502000116001120036080000102004020040200402004020040
800242003915500402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100000502000116001120036080000102004020040200402004020040
8002420039155120402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100000502000116001120036080000102004020040200402004020040
800242003915600402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100000502000116001120036080000102004020040200402004020040
80024200391559264462580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100000502000116201120036080000102004020040200402004020040
8002420039155304025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001002005020001160011200361580000102004020040200402004020040
800242003915500402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100000502000116001120036080000102004020040200402004020040
80024200391554320402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100000502000116001120036080000102004020040200402004020040
800242003915500402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100000502000116001120036080000102004020040200402004020040
80024200391552730402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100000502000116001120036080000102004020040200402004020040