Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRINT32Z (vector, 4S)

Test 1: uops

Code:

  frint32z v0.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723110220225472510001000100039816013018303730372414328951000100010003037303711100110002077416442629100030383038303830383038
1004303723111229625472510001000100039816013018303730372414328951000100010003037303711100110000077416442629100030383038303830383038
1004303724110227325472510001000100039816003018303730372414328951000100010003037303711100110000077416442629100030383038303830383038
1004303723111826825472510001000100039816013018303730372414328951000100010003037303711100110000077416442629100030383038303830383038
1004303724110211025472510001000100039816003018303730372414328951000100010003037303711100110000077416442629100030383038303830383038
1004303723110213125472510001000100039816003018303730372414328951000100010003037303711100110000077416442629100030383038303830383038
100430372311026825472510001000100039816003018303730372414328951000100010003037303711100110000077416442629100030383038303830383038
100430372311026825472510001000100039816003018303730372414328951000100010003037303711100110000077416442629100030383038303830383038
100430372411026825472510001000100039816003018303730372414328951000100010003037303711100110000077416442629100030383038303830383038
1004303723110228425472510001000100039816003018303730372414328951000100010003037303711100110000077416442629100030383038303830383038

Test 2: Latency 1->2

Code:

  frint32z v0.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)daddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003723300000103295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000710116011296330100001003003830038300383003830038
10204300372320000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000003710116011296330100001003003830038300383003830038
10204300372320000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000710116011296330100001003003830038300383003830038
10204300372330000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000710116011296330100001003003830038300383003830038
10204300372320000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000710116011296330100001003003830038300383003830038
10204300372330000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000710116011296330100001003003830038300383003830038
10204300372330000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000710116011296334100001003013330137301313008630038
1020430037233111044208161295472510100100100001001030060642798640300183003730037282713287621010020810331204101673008530085211020110099100100100001000010710116011296330100001003003830038300383003830038
102043003723300000254295472510100111100081001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000710116011296330100001003003830038300383003830038
102043003723300000612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000007101161512296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003723300000019329547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000006402163229629010000103003830038300383003830038
10024300372330000006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000006402163229629010000103003830038300383003830038
100243003723300000018929547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000006402162229629010000103003830038300383003830038
10024300372320000006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000006402163229629010000103003830038300383003830038
10024300372330000006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000906402162229629010000103003830038300383003830038
10024300372330000006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000006402162229629010000103003830038300383003830038
10024300372330000006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000006402162229629010000103003830038300383003830038
10024300372330000006129547251001010100001010000504277160130018300373003728291328767100102010000201000030037300371110021109101010000100000006402163229629010000103003830038300383003830038
10024300372320000006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000006402162229629010000103003830038300383003830038
10024300372330000006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000006402162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  frint32z v0.4s, v8.4s
  frint32z v1.4s, v8.4s
  frint32z v2.4s, v8.4s
  frint32z v3.4s, v8.4s
  frint32z v4.4s, v8.4s
  frint32z v5.4s, v8.4s
  frint32z v6.4s, v8.4s
  frint32z v7.4s, v8.4s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f243f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200491550000150058258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800000100000000111511801600200360800001002004020040200402004020040
8020420039155000000030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800000100000030111511801600200360800001002004020040200402004020040
8020420039155000060072258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800000100000030111511801600200360800001002004020040200402004020040
8020420039156000060030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800000100000000111511801600200360800001002004020040200402004020040
8020420039155000000030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800000100000000111511801600200360800001002004020040200402004020040
8020420039156000000030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800000100000000111511801600200360800001002004020040200402004020040
8020420039155000000030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800000100000000111511801600200360800001002004020040200402004020040
8020420039155000000030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800000100000000111511801600200360800001002004020040200402004020040
8020420039156000000030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800000100000000111511801600200360800001002004020040200402004020040
8020420039155000090030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800000100000000111511801600200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)dbddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391550102082258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001000502001616017720036080000102004020040200402004020040
800242003915500040258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001000502001716017620036080000102004020040200402004020040
8002420039156030402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010005020014160171720036080000102004020040200402004020040
800242003916109040258001010800001080000506400001020020200392003999963100198001020800002080000200392003911800211091010800001000502001716017820036080000102004020040200402004020040
8002420039156042040518001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001010502008160171720036080000102004020040200402004020040
80024200391550120402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010005020014160151520036080000102004020040200402004020040
8002420039156015040258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001004755020017160161620036080000102004020040200402004020040
8002420039155015040258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001000502001716017820036080000102004020040200402004020040
80024200391550210402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010005020017160161620036080000102004020040200402004020040
800242003915502730402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010005020814160171720036080000102004020040200402004020040