Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRINT64X (vector, 4S)

Test 1: uops

Code:

  frint64x v0.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230006125472510001000100039816013018303730372414328951000100010003037303711100110000073216112629100030383038303830383038
10043037240006125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037240006125472510001000100039816003018303730372414328951150100010003037303711100110000073116112629100030383038303830383038
10043037240006125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037230006125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037240006125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372400126125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037240006125472510001000100039816003018303730372414328951150100010003037303711100110000073116112629100030383038303830383038
10043037230006125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037240006125472510001000100039816013018303730372414328951000100010003037303711100110001073116112629100030383086303830383038

Test 2: Latency 1->2

Code:

  frint64x v0.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)0f18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003723200000000027329547251010010010000100101505004277160030018030037300372826432874510100200100002001000030037300371110201100991001001000010000000710011611296330100001003003830038300383003830038
10204300372320000000006129547251010010010000100100005004277160030018030037300372826432874510100200100002001000030037300371110201100991001001000010000100710011611296330100001003003830038300383003830038
10204300372330000000006129547251010010010000100100005004277160130018030037300372826432874510100200100002001000030037300371110201100991001001000010000000710011611296330100001003003830038300383003830038
10204300372330000000008429547251010010010000100100005004277160030018030037300372826432874510100200100002001000030037300371110201100991001001000010000000710011611296330100001003003830038300383003830038
102043003723300000000014729547251010010010000100100005004277160030018030037300372826432874510100200100002001000030037300371110201100991001001000010000000710011611296330100001003008430038300383003830038
102043003723300000000092229547251010010010000100100005004277160130018030037300372826432874510100200100002001000030037300371110201100991001001000010000100710011611296330100001003003830038300383003830038
1020430037233000000000180829547251010010010000100100005004277160030018030037300372826432874510100200100002001000030037300371110201100991001001000010000100710011611296330100001003003830038300383003830038
102043003723300000012008801852129466212102321521008815511650740429200313037803051330561283015128940118002381177623211653305143056311110201100991001001000010024143042395813118223008939100001003051930565305643056330565
10204305162360010910118879206622294741931022014710072146112007784290680130342030549304182829752288961149723011488228113253054830464911020110099100100100001002002161059050282212980823100001003003830038300383003830038
1020430037233110067795880021529547251010010010000100100005004277160030018030037300372826432874510100200100002001000030037300841110201100991001001000010000000710011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)030918191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243008522512206129547251001810100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000640316332962910000103003830038300383003830038
100243003722500006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000640316332962910000103003830038300383003830038
100243003722500006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000640316332962910000103003830038300383003830038
100243003722500001451295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000120640316332962910000103003830038300383003830038
100243003722400006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000640316332962910000103003830038300383003830038
1002430037225000971329547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000640316332962910000103003830038300383003830038
1002430037225000088129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000640316332962910000103003830038300383003830038
1002430037225000090229547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000640316332962910000103003830038300383003830038
1002430037225000083729547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000640316332962910000103003830038300383003830038
1002430037225000014729547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100300640316332962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  frint64x v0.4s, v8.4s
  frint64x v1.4s, v8.4s
  frint64x v2.4s, v8.4s
  frint64x v3.4s, v8.4s
  frint64x v4.4s, v8.4s
  frint64x v5.4s, v8.4s
  frint64x v6.4s, v8.4s
  frint64x v7.4s, v8.4s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f5051schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200391550304258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000011151181620036800001002004020040200402004020040
80204200391560300258010810080008100800205006401322002020039200399977699908012020080032200800322024720039118020110099100100800001001011151181620036800001002004020040200402004020040
80204200391550300258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000011151181620036800001002004020040200402004020040
802042003915584590258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000011151181620036800001002004020040200402004020040
80204200391550300258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000011151181620036800001002004020040200402004020040
80204200391550300258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000011151181620036800001002004020040200402004020040
80204200391550300258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000011151181620036800001002004020040200402004020040
80204200391550300258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000011151181620036800001002004020040200402004020040
80204200391550300258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000011151181620036800001002004020040200402004020040
80204200391550300258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000011151181620036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)accfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)ddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420051161004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000502000007169520036080000102004020040200402004020040
80024200391550040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010005020000061611620036080000102004020040200402004020040
80024200391550040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010005020000081610520036080000102004020040200402004020040
80024200391550040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010005020000071641020036080000102004020040200402004020040
8002420039155004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000502000006166520036080000102004020040200402004020040
8002420039155004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000502000003163520036080000102004020040200402004020040
80024200391550013525800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000502000014165520036080000102004020040200402004020040
80024200391560040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010005020000012165620036080000102004020040200402004020040
80024200391550040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010005020000011165620036080000102004020040200402004020040
80024200391500040258009410800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010005020000041641020036080000102004020040200402004020040