Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRINT64Z (vector, 4S)

Test 1: uops

Code:

  frint64z v0.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303724010325472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303724010325472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303724025125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110002073116112629100030383038303830383038
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110001073116112629100030383038303830383038
100430372536125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  frint64z v0.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003723300000210061295472510100100100001001000050042771600530018300373003728264032874510100200100002001000030037300371110201100991001001000010000000007100011611296330100001003003830038300383003830038
10204300372320000000061295472510100100100001001000050042771600030018300373003728264032874510100200100002001000030037300371110201100991001001000010000010007105011611296330100001003003830038300383003830038
102043003723300003180061295472510100100100001001000050042771600030018300373003728264032874510100200100002001000030037300371110201100991001001000010000000007100011611296330100001003003830038300383003830038
10204300372320000000061295472510100100100001001000050042771600030018300373003728264032874510100200100002001000030037300371110201100991001001000010000000007100011611296330100001003003830038300383003830038
10204300372330000000061295472510100100100001001000050042771601530018300373003728264032874510100200100002001000030037300371110201100991001001000010000000007100111611296330100001003003830038300383003830038
10204300372330000000061295472510100100100001001000050042771601530018300373003728264032874510100200100002001000030037300371110201100991001001000010000000007100011611296330100001003003830038300383003830038
1020430037233000003300536295472510100100100001001000050042771601530018300373003728264032874510100200100002001000030037300371110201100991001001000010000000007105111611296330100001003003830038300383003830038
102043003723300003300061295472510100100100001001000050042771600030018300373003728264032874510100200100002001000030037300371110201100991001001000010000010007105111611296330100001003003830038300383003830038
10204300372330000000061295472510100100100001001000050042771600030018300373003728264032874510100200100002001000030037300371110201100991001001000010000000007105111611296330100001003003830038300853003830038
10204300372320000000061295472510100100100001001000050042771600030018300373003728264032874510100200100002001000030037300371110201100991001001000010000000007105111611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
100243003722500000612952925100101010000101015072427716013001830037300372828632876710462201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037225000007262954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
100243003722500009612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
100243003723200000612954725100101010000101000050427716013001830178300372828632876710010201048820100003003730037111002110910101000010010640216222962910000103003830038300383003830038
100243003722500000612954725100101010000101000050427716013001830037300372828632876710010201000022100003003730037111002110910101000010000640216222977310000103003830038300383003830038
10024300372251000121032954796100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010003640216222962910000103003830038300383003830038
100243003722500006612954725100201010000101000060427716013001830037300372828632876710010201016220100003003730037111002110910101000010000640216222962910000103003830038300383003830038
100243003722500000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010010640216222962910000103003830038300383003830038
1002430037225000012612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  frint64z v0.4s, v8.4s
  frint64z v1.4s, v8.4s
  frint64z v2.4s, v8.4s
  frint64z v3.4s, v8.4s
  frint64z v4.4s, v8.4s
  frint64z v5.4s, v8.4s
  frint64z v6.4s, v8.4s
  frint64z v7.4s, v8.4s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)030e181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d2map dispatch bubble (d6)dde0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042003915600030258010810080008100800205006401321520020200392003999776999080120200800322008003220039200391180201100991001008000010000111511851160200360800001002004020040200402004020040
802042003915500072258010810080008100800205006401321520020200392003999776999080120200800322008003220039200391180201100991001008000010000111511851160200360800001002004020040200402004020040
802042003915500030258010810080008100800205006401321520020200912003999776999080120200800322008003220039200391180201100991001008000010000111511851160200360800001002004020040200402004020040
802042003915500030258010810080008100800205006401321520020200392003999776999080120200800322008003220039200391180201100991001008000010000111511851160200360800001002004020040200402004020040
802042003915500030258010810080008100800205006401321520020200392003999776999080120200801382008003220039200391180201100991001008000010000111511801160200360800001002004020040200402004020040
802042003915500030258010810080008100800205006401321520020200392003999776999080120200800322008003220039200391180201100991001008000010000111511851160200360800001002004020040200402004020040
802042003915500030258010810080008100800205006401321520020200392003999776999080120200800322008003220039200391180201100991001008000010000111513451160200360800001002004020040200402004020040
8020420039155001230258010810080008100800205006401321520020200392003999776999080120200800322008003220039200391180201100991001008000010000111511851160200360800001002004020040200402004020040
802042003916100030258010810080008100800205006401321020020200392003999776999080120200800322008003220039200391180201100991001008000010010111511851160200360800001002004020040200402004020040
8020420090155001230258010810080008100800205006401321020020200392003999776999080120200800322008003220039200391180201100991001008000010000111511801160200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4651schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200511550000000515025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000005020516332003680000102004020040200402004020040
8002420039155000000040025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000000005020316322003680000102004020040200402004020040
8002420039156000000040025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000000005020316232003680000102004020040200402004020040
8002420039155000000040025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000005020316332003680000102004020040200402004020040
8002420039155000000040025800101080000108000050640000120022200392003999963100198001020800002080000200392003911800211091010800001000000005020216232003680000102004020040200402004020040
8002420039155000000040025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000000005020316232003680000102004020040200402004020040
8002420039155000000040025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000000005020316322003680000102004020040200402004020040
8002420039155000000040025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000005020316332007880000102004020040200402004020040
8002420039155000060040025800101080097108000050640000120020200392003999963100198001020803072080624203022034871800211091010800001022010283805124480442027580000102024620397203452034220343
800242034015801268046160306308280700128058510806235064490802025920354202911005228101778065020804152080732204012034771800211091010800001020000333005020316322003680000102004020040200402011520040