Firestorm: FRINTA (scalar, H) measurements

Code:

  frinta h0, h0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	0	0	61	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	2	0	2	0	0	0	73	2	16	2	2	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	3	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	73	2	16	2	2	2645	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	61	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	73	2	16	2	2	2629	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	61	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	73	2	16	2	2	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	0	3	0	73	2	16	2	2	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	73	2	16	2	2	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	73	2	16	2	2	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	73	2	16	2	2	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	73	2	16	2	2	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2547	25	1008	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	2	17	4	3	4	73	2	16	2	2	2629	1000	3038	3085	3038	3038	3122

Test 2: Latency 1->2

Code:

  frinta h0, h0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	233	0	0	0	3	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	12	0	726	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	12	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	3	0	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	61	29547	97	10100	100	10000	100	10000	662	4277160	1	30018	30037	30037	28277	3	28745	10100	200	10000	216	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	3	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	1	0	0	0	1346	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	3	1	29633	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch call indir mispred nonspec (ca)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	241	0	0	0	0	0	27	0	291	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	3	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	0	0	298	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30131	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	0	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30132	30086	30038
10024	30178	234	0	1	0	0	3	0	0	853	29547	25	10010	10	10000	10	10000	50	4277160	0	30090	30225	30132	28286	3	28840	10464	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	9	0	0	0	640	2	16	2	2	29629	0	10000	10	30225	30086	30181	30038	30133
10024	30037	233	0	1	0	0	0	0	0	886	29547	25	10010	10	10000	10	10000	50	4277160	0	30090	30073	30037	28286	8	28805	10010	20	10000	20	10162	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	2	0	0	0	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	0	0	210	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10022	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	0	0	149	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	1	706	3	62	2	4	29775	1	10000	10	30134	30227	30085	30038	30224
10024	30228	233	0	0	1	0	4	0	136	2707	29511	100	10026	10	10032	11	10600	50	4277160	1	30162	30037	30225	28298	21	28844	10615	22	10000	20	10329	30225	30228	5	1	10021	10	9	10	10	10000	10	0	6	2	0	2	11130	0	0	0	640	2	16	2	2	29629	0	10000	10	30749	30312	30086	30038	30133
10024	30226	241	0	0	0	0	0	0	0	789	29547	25	10010	10	10000	10	10000	66	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	33480	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30083	233	0	0	0	0	0	0	0	167	29493	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	232	0	0	0	0	0	0	0	226	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	24	12131	30	11316	30646	30497	15	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038

Test 3: throughput

Count: 8

Code:

  frinta h0, h8
  frinta h1, h8
  frinta h2, h8
  frinta h3, h8
  frinta h4, h8
  frinta h5, h8
  frinta h6, h8
  frinta h7, h8

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dc	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20058	150	0	0	0	0	0	30	25	80108	100	80008	123	80020	500	640132	20020	20039	20039	9977	6	9990	80120	202	80032	200	80032	20039	20096	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	1	1	1	5118	0	16	0	1	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	1	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	1	1	1	5118	0	16	1	1	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	2	0	1	0	3	0	1	1	1	5137	0	28	0	0	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20090	150	0	0	1	12	0	30	25	80108	100	80008	100	80020	500	640132	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	1	1	1	5118	0	16	0	0	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	39	0	72	25	80108	100	80008	100	80020	500	640132	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	2	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	1	1	1	5118	0	16	0	0	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	1	1	1	5118	0	16	0	0	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	12	0	30	25	80108	100	80008	100	80020	500	640132	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	1	1	1	5118	0	16	0	0	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	147	264	58	25	80108	100	80008	100	80020	500	640132	20020	20039	20089	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	3	0	1	1	1	5118	0	16	0	0	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	149	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	1	1	1	5118	0	16	0	0	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	1	1	1	5118	0	16	0	1	0	20036	0	80000	100	20040	20040	20040	20040	20040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cf	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20039	155	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5020	0	0	13	16	3	3	20036	0	0	80000	10	20040	20040	20040	20040	20040
80024	20039	156	0	0	0	12	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5020	0	0	6	16	4	4	20036	0	0	80000	10	20040	20040	20040	20040	20040
80024	20039	155	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5020	0	0	6	16	4	4	20036	0	0	80000	10	20040	20040	20040	20040	20040
80024	20039	161	0	0	0	18	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5020	0	0	7	16	3	3	20036	0	0	80000	10	20040	20040	20040	20040	20040
80024	20039	155	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5020	0	0	5	16	4	5	20036	0	0	80000	10	20040	20040	20040	20040	20040
80024	20039	155	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5020	0	0	4	16	4	4	20036	0	0	80000	10	20040	20040	20040	20040	20040
80025	20039	155	0	0	0	0	0	103	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5020	0	0	6	16	4	4	20036	0	0	80000	10	20040	20040	20040	20040	20040
80024	20039	156	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5020	0	0	6	16	3	3	20036	0	0	80000	10	20040	20040	20040	20040	20040
80024	20039	155	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5020	0	0	4	16	4	3	20036	0	0	80000	10	20040	20040	20040	20040	20040
80024	20039	155	0	0	0	0	0	82	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5020	0	0	4	16	5	4	20036	0	0	80000	10	20040	20040	20040	20040	20040

FRINTA (scalar, H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations