Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRINTI (scalar, S)

Test 1: uops

Code:

  frinti s0, s0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372408225472510001000100039816013018303730372414328951000100010003037303711100110001073216112629100030383038303830383038
1004303724014725472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372406125472510001000100039816003018303730372414328951000100010003037303711100110000373116112629100030383038303830383038
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110001373116112629100030383038303830383038
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303724186125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383086303830383038
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  frinti s0, s0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003723300012061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000710011611296330100001003003830038300383003830038
102043003723200011117661295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000710011611296330100001003003830038300383003830038
10204300372330000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000710011611296330100001003003830038300383003830038
10204300372850000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000710011611296330100001003003830038300383003830038
10204300372330000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000710011611296330100001003003830038300383003830038
10204300372320000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000710011611296330100001003003830038300383003830038
102043003723200000726295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000742111611296330100001003003830038300383003830038
102043003723300000612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010046710011611296330100001003003830038300383003830038
10204300372410000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000710011611296330100001003003830038300383003830038
10204300372330000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000710011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000000023129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000000006402162229629010000103003830038300383003830038
100243003722400000006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000000006402162229629010000103003830038300383003830038
100243003722500000006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000000006402162229629010000103003830038300383003830038
100243003722400000006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100001000106402162229629010000103003830038300383003830038
1002430037224000000010529547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000000006402162229629010000103003830038300383003830038
100243003722500100006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000000006402162229629010000103003830038300383003830038
1002430037224000000012629547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000000006402162229629010000103003830038300383003830038
100243003722500000006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000000006402162229629010000103003830038300383003830038
100243003722500000006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000000006402162229629010000103003830038300383003830038
1002430037225000000010329547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000000006402162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  frinti s0, s8
  frinti s1, s8
  frinti s2, s8
  frinti s3, s8
  frinti s4, s8
  frinti s5, s8
  frinti s6, s8
  frinti s7, s8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200611560000000695258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000000000111511801600200360800001002004020040200402004020040
8020420039155000000030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000000000111511801600200360800001002004020040200402004020040
8020420039155000090030258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100000010000111511801620200360800001002004020040200402004020040
8020420039155000000030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000000000111511801700200360800001002004020040200402004020040
8020420039161000000030258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100000000000111511801600200360800001002004020040200402004020040
8020420039155000000030258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100000000000111511801600200360800001002004020040200402004020040
8020420039155000000030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000000000111511801600200360800001002004020040200402004020040
8020420039155000000030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000000000111511801600200360800001002004020040200402004020040
8020420039155000000030258010810080008100800205006401321200202003920039997769990801202008013820080032200392003911802011009910010080000100000000000111511801600200360800001002004020040200402004020040
8020420039155000000058258021610080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100020004000111511801600200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200401550000040258001010800001080000506400001020020200392003999963100198001020800002080000200392003911800211091010800001000000000502001161120036080000102004020040200402004020040
80024200391550000040258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001000000000502001161120036080000102004020040200402004020040
80024200391550000040258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001000000000502001161120036080000102004020040200402004020040
800242003915500120040258001010800001080000506400001120020200392003999963100198001020800002080000200392003911800211091010800001000000000502001161120036080000102004020040200402004020040
80024200391550000040258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001000000000502001161120036080000102004020040200402004020040
80024200391550000040258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001022202001502001161120036080000102004020040200402004020040
80024200391610000040258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001000000000502001161120036080000102004020040200402004020040
80024200391550000040258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001000000000502001161120036080000102004020040200402004020040
800242003915600000325258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001000000000502001161120036080000102004020040200402004020040
80024200891560000040258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001000000000502001161120036080000102004020040200402004020040