Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRINTI (vector, 4H)

Test 1: uops

Code:

  frinti v0.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723000145254725100010001000398160130183037303724143289510001000100030373037111001100000073316222629100030383038303830383038
100430372400061254725100010001000398160130183037303724143289510001000100030373037111001100000073216222629100030383038303830383038
1004303724000175254725100010001000398160130183037303724143289510001000100030373037111001100001073216222629100030383038303830383038
1004303724001261254725100010001000398160130183037303724143289510001000100030373037111001100001073216222629100030383038303830383038
1004303724011261254725100010001000398160130183037303724143289510001000100030373037111001100000073216222629100030383038303830383038
100430372300061254725100010001000398160130183037303724143289510001000100030373037111001100000073216222629100030383038303830383038
1004303724000149254725100010001000398160130183037303724143289510001000100030373037111001100000073216222629100030383038303830383038
1004303723000444254725100010001000398160030183037303724143289510001000100030373037111001100001073216222629100030383038303830383038
100430372400061254725100010001000398160130183037303724143289510001000100030373037111001100000073216222629100030383038303830383038
100430372300061254725100010001000398160130183037303724143289510001000100030373037111001100000073216222629100030383038303830383038

Test 2: Latency 1->2

Code:

  frinti v0.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037233000000171295472510100100100001001000050042771600300183003730037282717287411010020010008200100083003730037111020110099100100100001000000111717016002964500100001003003830038300383003830038
1020430037282000000817295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000000710216112963300100001003003830038300383003830038
102043003723300000061295382510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000000710116112963300100001003003830038300383003830038
102043003723300000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000000710116112963300100001003003830038300383003830038
1020430037232000000251295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000000710116112963300100001003003830038300383003830038
102043003723200000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000100000710116112963300100001003003830038300383003830038
1020430037233000000160295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000000710116112963300100001003003830038300383003830038
10204300372330001200131295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000000710116112963300100001003003830038300383003830038
1020430037233000120061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000000710116112963300100001003003830038300383003830038
102043003723300000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000000710116112969900100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000124295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
100243003722500000546295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
100243003722500000444295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
100243003722500000448295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
100243003722500000124295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
10024300372250000061295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
100243003722500000191295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
100243003722500000475295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
100243003722500000441295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000000006402162229629210000103003830038300383003830038
100243003722500000518295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000000006402162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  frinti v0.4h, v8.4h
  frinti v1.4h, v8.4h
  frinti v2.4h, v8.4h
  frinti v3.4h, v8.4h
  frinti v4.4h, v8.4h
  frinti v5.4h, v8.4h
  frinti v6.4h, v8.4h
  frinti v7.4h, v8.4h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)0e18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420061160000000003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000002000111511811600200360800001002004020040200402004020040
8020420039155000006008625801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000000000111511801600200360800001002004020040200402004020040
8020420039155000000003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000000000111511801600200360800001002004020040200402004020040
80204200391550000000069525801081008000810080020500640132120020200392003999776999080120200800322008046020039200391180201100991001008000010020000000111511801600200360800001002004020040200402004020040
8020420039156000000003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000000000111511801600200360800001002004020040200402004020040
8020420039155008000003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000000000111511801600200360800001002004020040200402004020040
8020420039155000000003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000000000111511801600200360800001002004020040200402004020040
8020420039156000000003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000000000111511801600200360800001002004020040200402004020040
8020420039156000000003025801081008000810080020500640132020020200392003999776999080120200800322028003220039200391180201100991001008000010000000000111511801600200360800001002004020040200402004020040
8020420039155000000003025801081008000810080020500640132020020200392004999776999080120200800322008003220039200391180201100991001008000010000000000111511801600200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd2l1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420176156000483258001010800001080000506400000020109200392003999963100198021520802142080000200392003911800211091010800001000060502005316362007580000102015020093200892004020040
80024200391550132040258001010800001080000506400000120020200392003999963100198001020800002080000200392003911800211091010800001000000502000316232003680000102004020040200402004020040
800242003915500040258001010800001080000506400000120020200392003999963100198001020800002080000201932003911800211091010800001000000502010316322003680000102004020040200402004020040
800242003915500040258001010800001080000506400000120020200392003999963100198001020800002080000200392003911800211091010800001000000502000316232003680000102004020040200402004020040
800242003915500040258001010800001080000506400000120020200392003999963100198001020800002080000200392003911800211091010800001000000502000316322003680000102004020040200402004020040
800242003915500040258001010800001080000506400000120020200392003999963100198001020800002080000200392003911800211091010800001000000502000316232003680000102004020040200402004020040
8002420039155000402580010108000010800005064000001200202003920039999631001980010208000020800002003920039118002110910108000010000570502000416322003680000102004020040200402004020040
800242003915500040258001010800001080000506400000120020200392003999963100198001020800002080414200392003911800211091010800001000000502000316332007580000102004020040200402004020093
8002420039155000406080010108000010801065064000011200202003920039100057100198032220801062080000200392003911800211091010800001000100502000216332013080000102004020040200932010520040
800242003915600040258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001000000502000316322003680000102004020040200402004020040