Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRINTI (vector, 4S)

Test 1: uops

Code:

  frinti v0.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723061254725100010001000398160301830373037241432895100010001000303730371110011000010073324222664100030383038303830383038
1004303723661254725100010001000398160301830373037241432895100010001000303730371110011000000073216222629100030383038303830383038
1004303724061254725100010001000398160301830373037241432895100010001000303730371110011000000073216222629100030383038303830383038
1004303724061254725100010001000398160301830373037241432895100010001000303730371110011000003073216222629100030383038303830383038
1004303724661254725100010001000398160301830373037241432895100010001000308330371110011000000073216222629100030383038303830383038
1004303723061254725100010001000398160301830373037241432895100010001000303730371110011000000073216222629100030383038303830383038
1004303723061254725100010001000398160301830373037241432895100010001000303730371110011000000073216222629100030383038303830383038
1004303724061254725100010001000398160301830373037241432895100010001000303730371110011000200273216222629100030383038303830383038
1004303724061254725100010001000398160301830373037241432895100010001000303730371110011000000073216222629100030383038303830383038
10043037241261254725100010001000398160301830373037241432895100010001000303730371110011000000073216222629100030383038303830383038

Test 2: Latency 1->2

Code:

  frinti v0.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372330061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007101161129633100001003003830038300383003830038
10204300372330094295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007101161129633100001003003830038300383003830038
10204300372330061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000020007101161129633100001003003830038300383003830038
10204300372330061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007101161129633100001003003830038300383003830038
10204300372330061295472510100100100001001000050042771600300183003730037282643287651010020010000200100003003730037111020110099100100100001000000007101161129633100001003003830038300383003830038
102043003723201561295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000307101161129633100001003003830038300383003830038
10204300372320061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007101161129633100001003003830038300383003830038
10204300372330061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007101161129633100001003003830038300383003830038
10204300372320661295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000307101161129633100001003003830038300383003830038
10204300372330061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007101161129633100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243068924411414196288084482943715310100181008812107507142906800300183008430037282863287671001020100002010000300373003711100211091010100001000640216222962910000103003830038300383003830038
10024300372320000061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000640216222962910000103003830038300383003830038
10024300372330000061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000640216222962910000103003830038300383003830038
10024300372330000061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000640216222962910000103003830038300383003830038
10024300372320003061295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000640216222962910000103003830038300383003830038
10024300372330000061295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000640216222962910000103003830038300383003830038
10024300372330000061295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001010640224222962910000103003830038300383003830038
10024300372330000061295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000640216222962910000103003830038300383003830038
10024300372250000061295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000640216222962910000103003830038300383003830038
10024300372250000061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000640216222962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  frinti v0.4s, v8.4s
  frinti v1.4s, v8.4s
  frinti v2.4s, v8.4s
  frinti v3.4s, v8.4s
  frinti v4.4s, v8.4s
  frinti v5.4s, v8.4s
  frinti v6.4s, v8.4s
  frinti v7.4s, v8.4s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)fetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005915503025801081008000810080020500640132200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160200360800001002004020040200402004020040
802042003915503025801081008000810080020500640132200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160200360800001002004020040200402004020040
802042003915563025801081008000810080020500640132200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160200360800001002004020040200402004020040
802042003915503025801081008000810080020500640132200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160201590800001002004020040200402004020040
8020420039155050525801081008000810080020500640132200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160200360800001002004020040200402004020040
802042003915503025801081008000810080020500640132200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160200360800001002004020040200402004020040
802042003915503025801081008000810080020500640132200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160200360800001002004020040200402004020040
802042003915503025801081008000810080020500640132200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160200360800001002004020040200402004020040
8020420039155011425801081008000810080020500640132200202003920039997769990801202008003220080032200392003911802011009910010080000100005311151180160200360800001002004020040200402004020040
8020420039155123025801081008000810080020500640132200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005115500402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100005020616662003680000102004020040200402004020040
800242003916100402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100005020616652003680000102004020040200402004020040
800242003915600402580010108000010800005064000012002020039200399996710019800102080000208000020039200391180021109101080000100005020516662003680000102004020040200402004020040
8002420039156004025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001042005020516562003680000102004020040200402004020040
800242003915500402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100005020516542003680000102004020040200402004020040
8002420039155003252580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100005020416662003680000102004020040200402004020040
800242003915500402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100005020416542003680000102004020040200402004020040
800242003915500402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100005020516562003680000102004020040200402004020040
800242003915500402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100005020516562003680000102004020040200402004020040
800242003915600402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100005020616752003680000102004020040200402004020040