Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRINTM (scalar, S)

Test 1: uops

Code:

  frintm s0, s0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)1e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372300061254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
100430372300010325472510001000100039816003018303730372414328951000100010003037303711100110000116273116112629100030383038303830383038
100430372400061254725100010001000398160030183037303724143289510001000100030373037111001100000373116112629100030383038303830383038
1004303725000612547251000100010003981600301830373037241432895100010001000303730371110011000058073116112629100030383038303830383038
100430372400061254725100010001000398160030183037303724143289510001000100030373037111001100000373116112629100030383038303830383038
100430372400061254725100010081000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303723000612547251000100010003981600301830373037241432895100010001000303730371110011000024873116122629100030383038303830383038
100430372300061254725100010001000398160030183037303724143289510001000100030373037111001100000373116112629100030383038303830383038
100430372400069254725100010001000398160030183037303724143289510001000100030373037111001100000373116112629100030383038303830383038
1004303724000612547251000100010003981600301830373037241432895100010001000303730371110011000015173116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  frintm s0, s0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372330000000214295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000100071021622296330100001003003830038300383003830038
10204300372330000000812295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000003071021622296330100001003003830038300383003830038
102043003723300000004282954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000002801273422966624100001003026630278302293027730038
10204300372330000000465295472510100100100001001000050042771600300183003730037282643287451010020210000200100003003730037111020110099100100100001000000000071021622296330100001003003830038300383003830038
1020430037233000000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000000071021622296990100001003003830038300383003830038
1020430037233000000082295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000000071021622296330100001003003830038300383003830038
1020430037233000000061295472510100100100001001000050042771600300183003730084282643287451027620810000200100003003730037111020110099100100100001000000200271021622296330100001003003830038300383003830038
10204300372330000000103295472510100100100001001000054242771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000000071021622296330100001003003830038300383003830038
10204300372320000000179295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730085111020110099100100100001000000000071021622296330100001003003830038300383003830038
10204300372330000000726295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000000071021622296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18193a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722400000214295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010000000640216222962910000103003830038300383003830038
100243003722500000382295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010000000640216222962910000103003830038300383003830038
100243003722500000612952944100191110016111015071427851230054301313008328295112880410237221032320104983013330133311002110910101000010402028430640216322962910000103013430132301323008530038
10024300372251112161295472510010101001610100005042771603009030132301302829082880510312201016120101623008430085311002110910101000010300028000640216222962910000103003830038300383003830038
10024300372250000061295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010000130640216222962910000103003830038300383003830038
100243003722500000342295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010000000640216222962910000103003830038300383003830038
100243003722400000363295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010000000640216222962910000103003830038300383003830038
100243003722500000820295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010000000640216222962910000103003830038300383003830038
10024300372240000061295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010000000640216222962910000103003830038300383003830038
100243003722500000504295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010000000640216222962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  frintm s0, s8
  frintm s1, s8
  frintm s2, s8
  frintm s3, s8
  frintm s4, s8
  frintm s5, s8
  frintm s6, s8
  frintm s7, s8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)030f1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9facbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)fetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200391550019225801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010001115118016020036800001002004020040200402004020040
8020420039155003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010001115118116020036800001002004020040200402004020040
8020420039156003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010001115118016020036800001002004020040200402004020040
8020420039155003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010001115118016020036800001002004020040200402004020040
8020420039155003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010001115118016020036800001002004020040200402004020040
8020420039155009525801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010001115118016020036800001002004020040200402004020040
8020420039155003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010001115118016020036800001002004020040200402004020040
8020420039156003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010001115118016020036800001002004020040200402004020040
8020420039156003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010001115118016020036800001002004020040200402004020040
8020420039155003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010001115118016020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03091e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005015500016625800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000005020716632003680000102004020040200942004020040
80024200391560004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000005020316362003680000102004020040200402004020040
80024200391550004025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000005020616352003680000102004020040200402004020040
80024200391550608225800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000305020316352003680000102004020040200402004020040
80024200391550008225800101080000108000050640000120020200392003999963100198001020802102080000200392003911800211091010800001000005020516642003680000102004020040200402004020040
80024200391550004025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000005020616532003680000102004020040200402004020040
80024200391550004025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001010005020516532003680000102004020040200402004020040
80024200391560008225800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000005020516632003680000102004020040200402004020040
80024200391560004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000005020316362003680000102004020040200402004020040
8002420039155000163825800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000005020516352003680000102004020040200402004020040