Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRINTM (vector, 2D)

Test 1: uops

Code:

  frintm v0.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372300612547251000100010003981603018303730372414328951000100010003037303711100110001073316332629100030383038303830383038
1004303723091032547251000100010003981603018303730372414328951000100010003037303711100110000073316332629100030383038303830383038
1004303723012612547251000100010003981603018303730372414328951000100011623037303711100110000073316332629100030383038303830383038
1004303723001152547251000100010003981603018303730372414328951000100010003037303711100110000073316332629100030383038303830383038
100430372400612547251000100010003981603018303730372414328951000100010003037303711100110000073316332629100030383038303830383038
10043037230285612547251000100010003981603018303730372414328951000100010003037303711100110000073316332629100030383038303830383038
100430372400612547251000100010003981603018303730372414328951000100010003037303711100110000073316442626100030383038303830383038
10043037230147612547251000100010003981603018303730372414328951000100010003037303711100110000073316332629100030383038303830383038
100430372300612547251000100010003981603018303730372414328951000100010003037303711100110000073316332629100030383038303830383038
100430372400612547251000100010003981603018303730372414328951000100010003037303711100110000073316332629100030383038303830383038

Test 2: Latency 1->2

Code:

  frintm v0.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache miss ld (a3)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037232006129547251010010010000100100005004277160030018030037300372826432874510100200100002001000030037300371110201100991001001000010000007101161129633100001003003830038300383003830038
1020430037232006129547251010010010000100100005004277160030018030037300372826432874510100200100002001000030037300371110201100991001001000010000007101161129633100001003003830038300383003830038
1020430037233006129547251010010010000100100005004277160030018030037300372826432874510100200100002001000030037300371110201100991001001000010000007101161129633100001003003830038300383003830038
1020430037233006129547251010010010000100100005004277160030018030037300372826432874510100200100002001000030037300371110201100991001001000010000007101161129633100001003003830038300383003830038
1020430037232006129547251010010010000100100005004277160030018030037300372827132874510100200100002001000030037300371110201100991001001000010000007102161129633100001003003830038300383003830038
1020430037233006129547251010010010000100100005004277160030018030037300372826432874510100200100002001000030037300371110201100991001001000010000007101161129633100001003003830038300383003830038
1020430037233006129547251010010010000100100005004277160030018030037300372826432874510100200100002001000030037300371110201100991001001000010000007101161129633100001003003830038300383003830038
1020430037233006129547251010010010000100100005004277160030018030037300372826432874510100200100002001000030037300372110201100991001001000010000007101161129633100001003003830038300383003830038
1020430037232006129547251010010010000100100005004277160030018030037300372826432874510100200100002001000030037300371110201100991001001000010000007101161129705100001003003830038300383003830038
1020430037233006129547251010010010000100100005004277160030018030037300372826432874510100200100002001000030037300371110201100991001001000010000007101161129633100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l1i tlb fill (04)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225100612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000000640216222962910000103003830038300383003830038
1002430037225000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037211002110910101000010000000640216222962910000103003830038300383008530038
10024300372250007262954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000000640216222962910000103003830038300383003830038
1002430037225000612954725100101010000101000050427716003001830226300372828632876710010201000020100003003730037111002110910101000010000000640216222962910000103003830038300383003830038
10024300372250007262954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000000640216222962910000103003830038300383003830038
10024300372250007262954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000001640216222962910000103003830038300383003830038
1002430037225000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000000640216222962910000103003830038300383003830038
1002430037225000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000000640216222962910000103003830038300383003830038
1002430037225000612954725100101010000101000050427716003001830084300372828632876710010201000020100003003730037111002110910101000010000000640216222962910000103003830038300383003830038
1002430037225000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000000640216222962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  frintm v0.2d, v8.2d
  frintm v1.2d, v8.2d
  frintm v2.2d, v8.2d
  frintm v3.2d, v8.2d
  frintm v4.2d, v8.2d
  frintm v5.2d, v8.2d
  frintm v6.2d, v8.2d
  frintm v7.2d, v8.2d
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9facbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420071155050525801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010036111511801610200360800001002004020040200402004020040
802042003915512302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000111511801600200360800001002004020040200402004020040
802042003916101162580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000111511801600200360800001002004020040200402004020040
802042003915501042580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000111511801600200360800001002004020040200402004020040
80204200391550302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000111511801600200360800001002004020040200402004020040
802042003915502042580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001003111511801600200360800001002004020040200402004020040
80204200391550302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000111511801600200360800001002004020040200402004020040
802042003915612532580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000111511801600200360800001002004020040200402004020040
802042003915502062580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001003111511801600200360800001002004020040200402004020040
80204200391550302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000111511801600200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)18191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005015600000102258001010800001080000506400000120020200392003999960310019800102080000208000020039200391180021109101080000100000050200004160005420036080000102004020040200402004020040
80024200391550000054258001010800001080000506400000020020200392003999960310019800102080000208000020039200391180021109101080000100000050200006160006720036080000102004020040200402004020040
80024200391550000040258001010800001080000506400000020020200392003999960310019800102080000208000020039200391180021109101080000100000050200005160005420036080000102004020040200402004020040
80024200391560000040258001010800001080000506400000020020200392003999960310019800102080000208000020039200391180021109101080000100000050200006160006520036080000102004020040200402004020040
800242003915500000103258001010800001080000506400000020020200392003999967310019800102080000208000020039200391180021109101080000100000050200006160006520036080000102004020040200402004020040
800242003915500000600258001010800001080000506400000020020200392003999960310019800102080000208000020039200391180021109101080000100000050200005160007620036080000102004020040200402004020040
8002420039156000021633258001010800001080000506400000020020200392003999960310019800102080000208000020039200391180021109101080000100000050200005160007520036080000102004020040200402004020040
80024200391550000340258001010800001080000506400000020020200392003999960310019800102080000208000020039200391180021109101080000100010050200005160006520036080000102004020040200402004020040
80024200391550000040258001010800001080000506400000020020200392003999960310019800102080000208000020039200391180021109101080000100000050200005160005520036080000102004020040200402004020040
80024200391550000040258001010800001080000506400000020020200392003999960310019800102080000208000020039200391180021109101080000100000050200004160006620036080000102004020040200402004020040