Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRINTM (vector, 2S)

Test 1: uops

Code:

  frintm v0.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303724061254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303723061254725100010001000398160030183037303724143289510001000100030373037111001100020073116112629100030383038303830383038
1004303723061254725100010001000398160030183037307324143289510001000100030373037111001100000073116112629100030383038303830383038
1004303723089254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303723061254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303724061254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303723061254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303724061254725100010001000399512030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303724061254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303724061254725100010001000398160030183037303724143289510001000100030373037111001100030073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  frintm v0.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003723302512954725101001001000010010000500427716010300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007100011611296330100001003003830038300383003830038
10204300372320612954725101001001000010010000500427716010300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007100011611296470100001003003830038300383003830038
10204300372320612954725101001001000010010000500427716015300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007105511611296330100001003003830038300383003830038
10204300372330612954725101001001000010010000500427716010300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007100011611296330100001003003830038300383003830038
102043003723301562954725101001001000010010000500427716010300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007100011611296330100001003003830038300383003830038
10204300372330612954725101001001000010010000500427716010300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007100011611296330100001003003830038300383003830038
10204300372330612954725101001001000010010000500427716010300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007100011611296330100001003003830038300383003830038
10204300372330612954725101001001000010010000500427716010300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007105011611296330100001003003830038300383003830038
10204300372330612954725101101001000010010000500427716010300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007105011611296330100001003003830038300383003830038
10204300372320612954725101001001000010010000500427716005300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007100011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)daddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000266295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000064411160101029629010000103003830038300383003830038
10024300372250000026629547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100033006441116051029629010000103003830038300383003830038
10024300372240000023902954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010004200064411160101029629010000103003830038300383003830038
1002430037225000002541295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000064410160111129629010000103003830038300383003830038
10024300372250000021612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000000644816010829629010000103003830038300383003830038
100243003722500000266295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000064411160111029629010000103003830038300383003830038
100243003722500000266295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000064410160101029629010000103003830038300383003830038
100243003722500000262295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000064410160101029629010000103003830038300383003830038
10024300372250000026229547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000006441016010529629010000103003830038300383003830038
100243003722500000262295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000000064410160101029629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  frintm v0.2s, v8.2s
  frintm v1.2s, v8.2s
  frintm v2.2s, v8.2s
  frintm v3.2s, v8.2s
  frintm v4.2s, v8.2s
  frintm v5.2s, v8.2s
  frintm v6.2s, v8.2s
  frintm v7.2s, v8.2s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200591550000001582580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010000311151180160120036800001002004020040200402004020040
8020420039155000000742580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
802042003915500002705052580108100800081008002050064013220020200392003999776999080120200800322008003220039201911180201100991001008000010000011151180160020036800001002004020040200402004020040
80204200391600000003762580108100800081008002050064013220020200392019899776999080120200800322008003220039200395180201100991001008000010000011151180160020036800001002004020040200402004020040
80204200391550000001772580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010000311151180160020036800001002004020040200402004020040
80204200391550000001562580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
80204200391550000001142580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180161020036800001002004020040200402004020040
80204200391550000005222580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
80204200391560000003172580108100800081008002050064013220020200392003999776999080120200800322008003220039202411180201100991001008000010000011151180160020036800001002004020040200402004020040
8020420039155000000302580108100800081008002050064013220020200392003999776999080120200802412008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)dbddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242003915500000000402580010108000010800005064000012002002003920039999631001980010208000020800002003920039118002110910108000010000000050205160332003680000102004020040200402004020040
800242003915500000000402580010108000010800005064000002002002003920039999631001980010208000020800002003920039118002110910108000010000000050202160332003680000102004020040200402004020040
800242003915500000000632580010108000010800005064000002002002003920039999631001980010208000020800002003920039118002110910108000010000000050203160322003680000102004020040200402004020040
800242003915600000000402580010108000010800005064000012002002003920039999631001980010208000020800002003920039118002110910108000010000000050203160332003680000102004020040200402004020040
8002420039156000000004582580010108000010800005064000012002002003920039999631001980010208000020800002003920039118002110910108000010000000050203160242011880000102011520143200932004020199
8002420039156000000001772580010108000010800005064000002002002003920039999631001980010208000020800002003920039118002110910108000010000000050203160322003680000102004020040200402004020040
800242003915500000000612580010108000010800005064000002002002003920039999631001980010208000020800002003920039118002110910108000010000000050203160332003680000102004020040200402004020040
8002420039156000000001032580010108000010800005064000012002002003920039999631001980010208000020800002003920039118002110910108000010000000050203160332003680000102004020040200402004020040
8002420039155000000021072580010108000010800005064000002002002003920039999631001980010208000020800002003920039118002110910108000010000000050203160432003680000102004020040200402004020040
8002420039155000000001982580010108000010800005064000012002002003920039999631001980010208000020800002003920039118002110910108000010000000050203160332003680000102004020040200402004020040