Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRINTN (scalar, S)

Test 1: uops

Code:

  frintn s0, s0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230061254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
10043037230061254725100010001000398160030183037303724143289510001000100030373037111001100000373124112629100030383038303830383038
10043037230061254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303723019861254725100010001000398160030183037303724143289510001000100030373037111001100000094116112629100030383038303830383038
10043037230061254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
10043037230082254725100010001000398160030183037303724143289510001000100030373037111001100000073134112629100030383038303830383038
100430372401861254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
100430372400103254725100010001000399515030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
10043037240061254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303724015103254725100010001000398160030183037303724143289510001000100030373037111001100002073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  frintn s0, s0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372320000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000000071011611296330100001003003830038300383003830038
10204300372330000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000000071011611296330100001003003830038300383003830038
10204300372330000006129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000000071011611296330100001003003830038300383003830038
10204300372330000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000000071011611296330100001003003830038300383003830038
10204300372330000006129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000000073511611296330100001003003830038300383003830038
10204300372320000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000000071011611296330100001003003830038300383003830038
102043003723200000048329547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000000071011611296330100001003003830038300383003830038
10204300372330000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000000071011611296330100001003003830038300383003830038
102043003723300000022529547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000000071011611296330100001003003830038300383003830038
10204300372320000008229547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000100071011611296333100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000006403162229629010000103003830038300383003830038
100243003723200000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000206402162229629010000103003830038300383003830038
1002430037225000001052954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
100243003722500000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229667010000103003830038300383003830038
100243003722500000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
100243003722500000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
100243003722500000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
100243003722500000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
100243003722400000822954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
100243003722500000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  frintn s0, s8
  frintn s1, s8
  frintn s2, s8
  frintn s3, s8
  frintn s4, s8
  frintn s5, s8
  frintn s6, s8
  frintn s7, s8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc3branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420039155003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151184163320036800001002004020040200402004020040
8020420039155003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151184164320036800001002004020040200402004020040
8020420039155003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151183163320036800001002004020040200402004020040
8020420039155003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151183164320036800001002004020040200402004020040
8020420039156003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010010011151183163420036800001002004020040200402004020040
8020420039155003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151183163320036800001002004020040200402004020040
8020420039155003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151182162420036800001002004020040200402004020040
8020420039155003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151184162320036800001002004020040200402004020040
80204200391564303025801081008000810080020500640132020020200392003999776999080120200800322028003220039200391180201100991001008000010000011151183163320036800001002004020040200402004020040
80204200391550243025801081008000810080020500640132020023200392003999776999080120200800322008003220039200391180201100991001008000010000011151183162420036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)daddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391550000004025800101080000108000050640000002002002003920039999631001980010208000020800002003920039118002110910108000010000050201816016162003680000102004020040200402004020040
800242003916100000014325800101080000108000050640000012002002003920039999631001980010208000020800002003920039118002110910108000010000050201616016162003680000102004020040200402004020040
80024200391550000004025800101080000108000050640000012002002003920039999631001980010208000020800002003920039118002110910108000010000050201616016162003680000102004020040200402004020040
80024200391550000004025800101080000108000050640000012002002003920039999631001980010208000020800002003920039118002110910108000010000050201716016162003680000102004020040200402004020040
8002420039156000000402580010108000010800005064000001200200200392003999963100198001020800002080000200392003911800211091010800001000005020161606162003680000102004020040200402004020040
800242003915500000040258001010800001080000506400000120020020039200399996310019800102080000208000020039200391180021109101080000100000502061601662003680000102004020040200402004020040
8002420039156000000402580010108000010800005064000001200200200392003999963100198001020800002080000200392003911800211091010800001000005020161606162003680000102004020040200402004020040
80024200391550000004025800101080000108000050640000012002002003920039999631001980010208000020800002003920039118002110910108000010000050201716013132003680000102004020040200402004020040
8002420039155000000402580010108000010800005064000001200200200392003999963100198001020800002080000200392003911800211091010800001000005020161605162003680000102004020040200402004020040
800242003915500001770682580010108000010800005064000000200200200392003999963100198001020800002080000200392003911800211091010800001000005020161601552003680000102004020040200402004020040