Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRINTP (scalar, S)

Test 1: uops

Code:

  frintp s0, s0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723006125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723007525472510001000100039816013018303730372414328951000100010003037303711100110000373116112629100030383038303830383038
1004303723006125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030863038303830383038
1004303724006125472510001000100039951213018303730372414328951000100010003037303711100110008073116112629100030383086303830383038
1004303723006125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383085
10043037243015625472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303724006125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723006125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037231208225472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723006125472510001000100039816003018303730372414328951000100010003037303711100110000373316112629100030383038303830383038

Test 2: Latency 1->2

Code:

  frintp s0, s0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)l2 tlb miss data (0b)191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372330000006629547251010010010000100100005004277160130018300373003728264328745101002001000020010000300843018421102011009910010010000100000007101161129633100001003003830038300383003830038
10204300372320000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000007101161129633100001003003830038300383003830038
10204300372330000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000007101161129633100001003003830038300383003830038
10204300372320000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000007101161129633100001003003830038300383003830038
10204300372330000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000007101161129633100001003003830038300383003830038
102043003723300000072629547251010010010000100100005004277160130018300373003728264328745101002041000020010000300373003711102011009910010010000100000007101161129633100001003003830038300383003830038
10204300372330000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000007101161129633100001003003830038300383003830038
10204300372330000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000007101161129633100001003003830038300383003830038
10204300372330000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000007101161129707100001003003830038300383003830038
10204300372330000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000007101161129633100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010006403163329631010000103003830038300383003830038
1002430037225100612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010006403163329629010000103003830038300383003830038
1002430037225000612954725100101010000101000050427716003001830037300372828632876710010201000020101723003730037111002110910101000010106403163329629010000103003830038300383003830038
10024300372250007372954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010006403163329629210000103003830038300383003830038
10024300372250001032954725100101010000101000050427716013001830037300372828632876710010201000020104973018030085111002110910101000010006427163329629010000103003830038300383003830038
1002430037225000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010006403163329629010000103003830038300383003830038
1002430037225000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010006403163329629010000103003830038300383003830038
1002430037225000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010006403163329629010000103003830038300383003830038
1002430037225000612954725100101210000101000060427716013001830037300372828632876710010201000020100003003730037111002110910101000010006403163329629010000103003830038300383003830038
1002430037225000622954725100101010000101000050427716013001830037300372828632876710010221000020100003003730037111002110910101000010006403163329629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  frintp s0, s8
  frintp s1, s8
  frintp s2, s8
  frintp s3, s8
  frintp s4, s8
  frintp s5, s8
  frintp s6, s8
  frintp s7, s8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200391560072727801161008001610080028500640196020029200482004899761099868012820080038200800382004920048118020110099100100800001000000222512903231120045800001002004920049200492005020050
802042004915503642680116100800161008002850064019612002920049200489976999868012820080038200800382004820048118020110099100100800001000000222512901232120045800001002004920049200492004920050
8020420049160007422680116100800161008002850064019602002920048200499976999868012820080038200801422010820049118020110099100100800001000000222512901231120045800001002005020049200502005020049
8020420049155008092680116100800161008002850064019602002920048200499976999868012820080038200800382004820048118020110099100100800001000000222512901231120045800001002005020049200492004920049
8020420048156006427801161008001610080028500640196020029200492004899761099868012820080038200800382004920049118020110099100100800001000000222512801231120045800001002004920050200492004920049
80204200481550090026801161008001610080028500640196020029200482004999761099868012820080038200800382004820048118020110099100100800001000000222512801231120046800001002005020050200492004920050
80204200481550010132680116100800161008002850064019612002920048200489976999868012820080038200800382004820049118020110099100100800001000000222512901231120046800001002005020049200492004920049
8020420048156009772680116100800161008002850064019602002920048200499976999868012820080038200800382004820048118020110099100100800001000000222512801231120045800001002005020049200492004920050
80204200481610088027801161008001610080028500640196120029200492004899761099868012820080038200800382004920048118020110099100100800001000030222512801231120045800001002004920049200492004920050
8020420048156008852680116100800161008002850064019602002920048200489976999868012820080038200800382004820048118020110099100100800001000000222512901231120045800001002004920049200492004920049

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391550005492580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100005020916342003680000102004020040200402004020040
8002420039155000402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100005020416242003680000102004020040200402004020040
800242003915500011812580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100005020416352003680000102004020040200402004020040
80024200391560001242580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100105020616242003680000102004020040200402004020040
8002420039156000402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100005020216242003680000102004020040200402004020040
8002420039161100402580010108000010800005064164002002020039200399996310019800102080000208000020039200391180021109101080000100005020416422003680000102004020040200402004020040
8002420039155000409780010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100005020216242003680000102004020040200402004020040
8002420039155000402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100005020216242003680000102004020040200402004020040
8002420039155000402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100005020416532003680000102004020040200402004020040
80024200391550078402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100005020316422003680000102004020040200402004020040