Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRINTP (vector, 8H)

Test 1: uops

Code:

  frintp v0.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk instruction (07)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372400822547251000100010003981600301830373037241432895100010001000303730371110011000000073116112629100030383038303830383038
100430372400612547251000100010003981600301830373037241432895100010001000303730371110011000000073116112629100030383038303830383038
100430372400612547251000100010003981600301830373037241432895100010001000303730371110011000000073116112629100030383038303830383038
100430372300612547251000100010003981600301830373037241432895100010001000303730371110011000020073116112629100030383038303830383038
100430372300612547251000100010003981600301830373037241432895100010001000303730371110011000000073116112629100030383038303830383038
100430372400612547251000100010003981601301830373037241432895100010001000303730371110011000000073116112629100030383038303830383038
100430372400612547251000100010003981601301830373037241432895100010001000303730371110011000000073116112629100030383038303830383038
100430372400612547251000100010003981600301830373037241432895100010001000303730371110011000000073116112629100030383038303830383038
100430372400612547251000100010003981600301830373037241432895100010001000303730371110011000000073116112629100030383038303830383038
1004303724012612547251000100010003981600301830373037241432895100010001000303730371110011000001073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  frintp v0.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)1e1f3f4e5051schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225020061295472251010010010000100100005004277160130018030037300372826432874510100200100002141000030037300371110201100991001001000010000071021622296330100001003003830038300383003830038
102043003722502570612954702510100100100001001000050042771600300180300373003728264328745101002001000020010000300373003711102011009910010010000100011273521622296330100001003003830038300383003830038
1020430037225020061295470251010010010000100100005004277160030018030037300372826432874510100200100002001000030037300371110201100991001001000010000071021622296330100001003003830038300383003830038
102043003722502120061295470251010010010000100100005004277160130018030037300372826432874510100200100002001000030037300371110201100991001001000010000071021622296330100001003003830038300383003830038
1020430037225020061295470251010010010000100100005004277160030018030037300372826432874510100200100002001000030037300371110201100991001001000010000071021622296330100001003003830038300383003830038
10204300372250212061295470251010010010000100100005004277160130018030037300372826432874510100200100002001000030037300371110201100991001001000010000071021622296330100001003003830038300383003830038
1020430037225020061295470251010010010000100100005004277160130018030037300372826432874510100200100002001000030037300371110201100991001001000010000071021622296330100001003003830038300383003830038
102043003722502300536295470251010010010000100100005004277160030018030037300372826432874510100200100002001000030037300371110201100991001001000010000071021622296330100001003003830038300383003830038
1020430037224020061295470251010010010000100100005004277160130018030037300372826432874510100200100002001000030037300371110201100991001001000010000071021622296330100001003003830038300383003830038
102043003722502240103295470251010010010000100100005004277160030018030037300372826432874510100200100002001000030037300371110201100991001001000010000071021622296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)191e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000384129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006402162229629010000103003830038300383003830038
100243003722410006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006402162229629010000103003830038300383003830038
1002430037225000019329547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006402162229629010000103003830038300383003830038
100243003722400006129547251001010100001010000504277160030018300373003728286328767101592010000201000030037300371110021109101010000100006402162229629010000103003830038300383003830038
1002430037235000015129547251001810100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006404162229629010000103003830038300383003830038
100243003722400006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006402161229629010000103003830038300383003830038
100243003722500006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006402162229629010000103003830038300383003830038
100243003722500006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006402162229629010000103003830038300383003830038
100243003722500006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006402162229629010000103003830038300383003830038
100243003722400006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006402162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  frintp v0.8h, v8.8h
  frintp v1.8h, v8.8h
  frintp v2.8h, v8.8h
  frintp v3.8h, v8.8h
  frintp v4.8h, v8.8h
  frintp v5.8h, v8.8h
  frintp v6.8h, v8.8h
  frintp v7.8h, v8.8h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420058155001230258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160020036800001002004020040200402004020040
802042003915500030258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160020036800001002004020040200402004020040
802042003915500030258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160020036800001002004020040200402004020040
802042003915500030258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100100011151180160020036800001002004020040200402004020040
802042003915500030258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160020036800001002004020040200402004020040
802042003915500030258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160020036800001002004020040200402004020040
802042003915500030258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160020036800001002004020040200402004020040
802042003915500030258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100023011151180160020036800001002004020040200402004020040
802042003915500030258010810080008100800205006401320200572003920039997769990801202008003220080032200392003911802011009910010080000100000011151182162020036800001002004020040200402004020040
802042003915500030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048155072822580010108000010800005064000012002002003920039999631001980010208000020800002003920039118002110910108000010105020416332003680000102004020040200402004020040
800242003915600402580010108000010800005064000002002002003920039999631001980010208032120800002003920039118002110910108000010035020216552003680000102004020040200402004020040
800242003915510402580010108000010800005064000002002002003920039999631001980010208000020800002003920039118002110910108000010035020316552003680000102004020040200402004020040
800242003915503402580010108000010800005064000002002002003920039999631001980010208000020800002003920039118002110910108000010005020516362003680000102004020040200402004020040
8002420039155027402580010108000010800005064000002002002003920039999631001980010208000020800002003920039118002110910108000010005020316532003680000102004020040200402004020040
800242003915500402580010108000010800005064000002002002003920039999631001980010208000020800002003920039118002110910108000010105020316552003680000102004020040200402004020040
800242003915600402580010108000010800005064000002002002003920039999631001980010208000020800002003920039118002110910108000010005020516232003680000102004020040200402004020040
800242003915500402580010108000010800005064000002002002003920039999631001980010208000020800002003920039118002110910108000010095020316332003680000102004020040200402004020040
800242003915500402580010108000010800005064000002002002003920039999631001980010208000020800002003920039118002110910108000010005020616532003680000102004020040200402004020040
8002420039155039402580010108000010800005064000002002002003920039999631001980010208000020800002003920039118002110910108000010005020216232003680000102004020040200402004020040