Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRINTX (scalar, S)

Test 1: uops

Code:

  frintx s0, s0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723010325472510001000100039816003018303730372414328951000100010003037303711100110001073216222629100030383038303830383038
100430372206125472510001000100039816003018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
1004303723010325472510001000100039816003018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
10043037231211725472510001000100039816003018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
100430372208225472510001000100039816003018303730372414328951000100010003037303711100110001073216222629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000373216222629100030383038303830383038
1004303722010325472510001000100039816003018303730372414328951000100010003037303711100110000073216222629100030383038303830383038

Test 2: Latency 1->2

Code:

  frintx s0, s0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722512103295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001001307101161129633100001003003830038300383003830038
102043003722512103295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000307101161129633100001003003830038300383003830038
102043003722512308295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001001307101161129633100001003003830038300383003830038
102043003722512103295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000307101161129633100001003003830038300383003830038
102043003722512103295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000307101161129633100001003003830038300383003830038
102043003722512103295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001001307101161129633100001003003830038300383003830038
102043003722512103295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001001307101161129633100001003003830038300383003830038
10204300372251261295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001001307101161129633100001003003830038300383003830038
10204300372241261295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001001307101161129633100001003003830038300383003830038
102043003722512103295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000007101161129633100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722403612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
100243003722500612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000640216132962910000103003830038300383003830038
100243003722500612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
10024300372250393822954725100101010016101015050427716003001830037300372828632876710010201000020100003003730084111002110910101000010013640216422962910000103003830038300383003830038
100243003722500612954725100291010000101015050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
100243003722500612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
100243003722400612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
100243003722500612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037225012612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
100243003722500612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  frintx s0, s8
  frintx s1, s8
  frintx s2, s8
  frintx s3, s8
  frintx s4, s8
  frintx s5, s8
  frintx s6, s8
  frintx s7, s8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420059150000012072258010810080008100800205006401321200200200392003999776999080120200800322008003220039200391180201100991001008000010000100011151180160020036800001002004020040200402004020040
8020420039150000012072258010810080008100800205006401321200200200392003999776999080120200800322008003220039200391180201100991001008000010000103011151180160020078800001002014320145200402014720142
802042019615201324112646659980402100803041008033850064100802014102014320142999613100408033820080457200801402003920147318020110099100100800001002010258211151181460120036800001002020220144200952004020195
8020420246151003030618258010810080301100800205006401320200200200392003999966999080120200801452008003220039200391180201100991001008000010000100211151180160020074800001002004020040200402004020040
802042003915011436602643025805031008000810080020500640132120020020089200399986111007080436200800322008003220196200393180201100991001008000010000020011151180160020036800001002004020040200402004020040
8020420039150000090663258010810080008100800205006401321200200200392003999776999080120200800322008003220039200391180201100991001008000010000201418211351340160020036800001002004020040200402004020040
80204201911550000120294109805951048030710080545500640196120020020206200919976351001380128200800382008003820048200491180201100991001008000010000003022251281234120128800001002004920049200502005020050
802042004816000002402042780116100800161028002850064019612002902004820049100159998680128200800382008003820199200491180201100991001008000010004100022251291232120207800001002004920050200492005020050
802042004915501001209961388011610080016100800285006401961201140200482004899769998680128200800382008003820049200481180201100991001008000010000121436022251281231120045800001002004920049200502004920049
80204200481560003684368302268011610080016100801275006401961200290200482004899769998680128200800382008003820048200481180201100991001008000010000000022251281231120085800001002020220040201472009120040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005115000090402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100000050202165320036080000102004020040200402004020040
800242003915000000402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100000050204164420036080000102004020040200402004020040
800242003915000000402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100000050203164420036080000102004020040200402004020040
800242003915000000402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100000050204164420036080000102004020040200402004020040
800242003915000000402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100000050204164420036080000102004020040200402004020040
800242003915010000402580010108000010801045064000012002020039200399996310019800102080000208000020039200391180021109101080000100000050205162320036080000102004020040200402004020040
800242003915000000402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100000050205165520036080000102004020040200402004020040
800242003915000000402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100000050204163420036080000102004020040200402004020040
800242003915000000402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100000050374293420089080000102010020140201502014320153
8002420089150122288104404980107108009710802025064081612006720102200921000581004780109208010520801052009220150318002110910108000010700480050375595520086080000102009120040201032004020040