Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRINTZ (vector, 2D)

Test 1: uops

Code:

  frintz v0.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372206125472510001000100039816030183037303724143289510001000100030373037111001100073116112629100030383038303830383038
100430372306125472510001000100039816030183037303724143289510001000100030373037111001100073116112629100030383038303830383038
100430372306125472510001000100039816030183037308424143289510001000100030373037111001100073116112629100030383038303830383038
1004303722015625472510001000100039816030183037303724143289510001000100030373037111001100073116112629100030383038303830383038
100430372306125472510001000100039816030183037303724143289510001000100030373037111001100073116112629100030383038303830383038
100430372306125472510001000100039816030183037303724143289510001000100030373037111001100073116112629100030383038303830383038
100430372206125472510001000100039816030183037303724143289510001000100030373037111001100073116112629100030383038303830383038
100430372206125472510001000100039816030183037303724143289510001000100030373037111001100073116112629100030383038303830383038
1004303722366125472510001000100039816030183037303724143289510001000100030373037111001100073116112629100030383038303830383038
100430372206125472510001000100039816030183037303724143289510001000100030373037111001100073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  frintz v0.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225061295472510100100100001001000050042771600300183003730037282717287401010020010008200100083003730037111020110099100100100001000001117170160029646100001003003830038300383003830038
10204300372252461295472510100100100001001000050042771600300183003730037282716287401010020010008200100083003730037111020110099100100100001000001117180160029645100001003003830038300383003830038
10204300372241261295472510100100100001001000050042771600300183003730037282717287411010020010008200100083003730037111020110099100100100001000001117170160029646100001003003830038300383003830038
1020430037225661295472510100100100001001000050042771600300183003730037282717287411010020010008200100083003730037111020110099100100100001000001117170160029706100001003003830038300383003830038
102043003722521961295472510100100100001001000050042771600300183003730037282716287401010020010008200100083003730037111020110099100100100001000001117180160029645100001003003830038300383003830038
1020430037225661295472510100100100001001000050042771600300183003730037282717287411010020010008200100083003730037111020110099100100100001000001117180160029646100001003003830038300383003830038
1020430037224661295472510100100100001001000050042771600300183003730037282716287401010020010008200100083003730037111020110099100100100001000001117180160029646100001003003830038300383003830038
10204300372252161295472510100100100001001000050042771600300183003730037282717287411010020010008200100083003730037111020110099100100100001000001117180160029645100001003003830038300383003830038
10204300372251861295472510100100100001001000050042771600300183003730037282716287401010020010008200100083003730037111020110099100100100001000001117170160029645100001003003830038300383003830038
10204300372252161295472510100100100001001000050042771600300183003730037282717287401010020010008200100083003730037111020110099100100100001000001117180160029646100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250270103295472510010101000010100005042771600300180300373003728286328767100102010000201000030037300371110021109101010000100001000640216222962910000103003830038300383003830038
1002430037225012061295472510010101000010100005042771601300183300373003728286328767100102010000201000030037300371110021109101010000100000030640216222962910000103003830038300383003830038
1002430037225000103295472510010101000010100005042771600300180300373003728286328767100102010000201000030037300371110021109101010000100000000640216222962910000103003830038300383003830038
10024300372250330103295472510010101000010100005042771600300180300373003728286328767100102010000201000030037300371110021109101010000100000000640216222962910000103003830038300383003830038
10024300372250240103295472510010101000010100005042771601300180300373003728286328767100102010000201000030037300371110021109101010000100000000640216222962910000103003830038300383003830038
10024300372250120103295472510010101000010100005042771601300180300373003728286328767100102010000201000030037300371110021109101010000100001030640216222962910000103003830038300383003830038
10024300372250300103295472510010101000010100005042771601300180300373003728286328767100102010000201000030037300371110021109101010000100001030640216222962910000103003830038300383003830038
10024300372250570768295472510010101000010100005042771600300180300373003728286328767100102010000201000030037300371110021109101010000100001030640216222962910000103003830038300383003830038
10024300372250120103295472510010101000010100005042771600300180300373003728286328767100102010000201000030037300371110021109101010000100000030640216222962910000103003830038300383003830038
10024300372250300103295472510010101000010100005042771601300180300373003728286328767100102010000201000030037300371110021109101010000100001000640216222962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  frintz v0.2d, v8.2d
  frintz v1.2d, v8.2d
  frintz v2.2d, v8.2d
  frintz v3.2d, v8.2d
  frintz v4.2d, v8.2d
  frintz v5.2d, v8.2d
  frintz v6.2d, v8.2d
  frintz v7.2d, v8.2d
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200611500333025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010020011151180161120045800001002005020050200502005020050
8020420048150006427801161008001610080028500640196020029200482004999769998680128200800382008003820048200481180201100991001008000010000022251291231120045800001002004920049200492004920049
8020420048150096426801161008001610080028500640196020029200482004999769998680128200800382008003820048200481180201100991001008000010000022251291231120046800001002004920049200492004920049
80204200491500126427801161008001610080028500640196120029200482004999769998680128200800382008003820048200481180201100991001008000010000022251291231120046800001002004920049200502004920049
802042004815002764268011610080016100800285006401960200292004920049997610998680128200800382008003820048200481180201100991001008000010000022251291231120046800001002004920049200492004920050
8020420049150036426801161008001610080028500640196020029200482004899769998680128200800382008003820048200491180201100991001008000010000022251291231120046800001002004920050200492004920050
80204200481500186426801161008001610080028500640196020029200482004899769998680128200800382008003820048200491180201100991001008000010000022251281231120046800001002005020050200502005020049
802042004815001210626801161008001610080028500640196020041200482004899769998680128200800382008003820048200481180201100991001008000010001322251291231120045800001002004920050200502005020049
8020420048150012106268011610080016100800285006401960200292004820048997610998680128200800382008003820048200491180201100991001008000010001322251281231120046800001002005020049200492005020049
802042004815006010626801161008001610080028500640196020029200482004999769998680128200800382008003820048200481180201100991001008000010000322251281231120045800001002004920049200492004920049

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005115001282258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001001305020121613122003680000102004020040200402004020040
800242003915002140258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001001005020141610142003680000102004020040200402004020040
800242003915001240258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001001005020131615152003680000102004020040200402004020040
80024200391500082258001010800001080000506400001020020200392003999963100198001020800002080000200392003911800211091010800001001005020121614142003680000102004020040200402004020040
8002420039150012402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010002705020121614162003680000102004020040200402004020040
80024200391500082258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001001305020141614132003680000102004020040200402004020040
80024200391500382258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001001005020141614142003680000102004020040200402004020040
800242003915002782258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001001305020121611112003680000102004020040200402004020040
800242003915001240258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001001305020111614142003680000102004020040200402004020040
80024200391500040258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001000305020111614132003680000102004020040200402004020040