Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRINTZ (vector, 2S)

Test 1: uops

Code:

  frintz v0.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk instruction (07)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303722006125472510001000100039816013018303730372414328951000100010003037303711100110001373216332629100030383038303830383038
10043037230126125472510001000100039816013018303730372414328951000100010003037303711100110000073316222629100030383038303830383038
1004303723006125472510001000100039816013018303730372414328951000100010003037303711100110000373316332629100030383038303830383038
1004303723106125472510001000100039816013018303730372414328951000100010003037303711100110001073316332629100030383038303830383038
10043037230012625472510001000100039816013018303730372414328951000100010003037303711100110000073316332629100030383038303830383038
100430372301212625472510001000100039816013018303730372414328951000100010003037303711100110000373316332629100030383038303830383038
1004303722008225472510001000100039816013018303730372414328951000100010003037303711100110001073316332629100030743038303830383038
10043037220010325472510001000100039816013018303730372414328951000100010003037303711100110001073316332629100030383038303830383038
1004303723008425472510001000100039816013018303730372414328951000100010003037303711100110001073316332629100030383038303830383038
1004303722008425472510001000100039816013018303730372414328951000100010003037303711100110000073316332629100030383038303830383038

Test 2: Latency 1->2

Code:

  frintz v0.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722400001032954725101001001000010010000500427716010300183003730037282643287451010020010000200100003003730037111020110099100100100001001371041161129633100001003003830038300383003830038
102043003722500001032954725101001001000010010000500427716014300183003730037282643287451010020010000200100003003730037111020110099100100100001001071041161129633100001003003830038300383003830038
1020430037225000122932954725101001001000010010000500427716004300183003730037282643287451010020010000200100003003730037111020110099100100100001000371041161129633100001003003830038300383003830038
102043003722500001032954725101001001000010010000500427716004300183003730037282643287451010020010000200100003003730037111020110099100100100001001371041161129633100001003003830038300383003830038
1020430037225000121032954725101001001000010010000500427716014300183003730037282643287451010020010000200100003003730037111020110099100100100001001371001161129633100001003003830038300383003830038
10204300372250000612954725101001001000010010000500427716010300183003730037282643287451010020010000200100003003730037111020110099100100100001001371001161129633100001003003830038300383003830038
102043003722500001032954725101001001000810010000500427716004300183003730037282643287451010020010000200100003003730037111020110099100100100001001371041161129633100001003003830038300383003830038
1020430085225000181452954725101001001000010010000500427716004300183003730037282643287451010020010000200100003003730037111020110099100100100001001671003161129633100001003003830038300383003830038
10204300372250007951452954725101001001000010010000500427812900300183003730037282643287451010020010000200101653003730037111020110099100100100001002671001161129633100001003003830038300383003830038
102043003723300001032954725101001001000010010000500427716000300183003730037282643287451010020010000200100003003730037111020110099100100100001000371001161129633100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722400254129547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000000644111611112962910000103003830038300383003830038
10024300372250026629547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000000644124111112962910000103003830038300383003830038
10024300372250027662954725100101010000101000050427716030018300373003728286328767100102010000201000030037300371110021109101010000100000064411161162962910000103003830038300383003830038
10024300372250026629547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000000644111611112962910000103003830038300383003830038
10024300372250026629547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000000644121611112962910000103003830038300383003830038
1002430037225012210829547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000000644111611112962910000103003830038300383003830038
1002430037225002662954725100101010000101000050427716030018300373003728286328767100102010000201000030037300371110021109101010000100010064412161162962910000103013230085300383003830038
10024300372250122662954725100101010008101000050427716030018300373003728286328767100102010000201000030037300371110021109101010000100000064411161162962910000103003830038300383003830038
10024300372250926629547251001010100001010000504278512300183003730037282863287671001020100002010000300373003711100211091010100001000127780644121611112962910000103003830038300383003830038
10024300372250026629547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000000644111611112962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  frintz v0.2s, v8.2s
  frintz v1.2s, v8.2s
  frintz v2.2s, v8.2s
  frintz v3.2s, v8.2s
  frintz v4.2s, v8.2s
  frintz v5.2s, v8.2s
  frintz v6.2s, v8.2s
  frintz v7.2s, v8.2s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042003915500000197258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001004234011151181161020089800001002004020040200402004020040
802042003915505000722580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
8020420039150001120722580108100800081008002050064013220153200392003999776999080120200800322008003220039200391180201100991001008000010010011151180160020036800001002004020040200402004020040
8020420039156000120722580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010013011151180160020036800001002004020040200402004020040
80204200391550001202922580108100801081008002050064013220020200392003999776999080120200800322008003220039200911180201100991001008000010003011151180160020036800001002004020040200402009420040
802042003915600012072925801081008000810080020500640132200202003920255997769990801202008056420080032200392003911802011009910010080000100312411151180160020036800001002004020040200402024120040
802042014115500040802872580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010016011151180160220036800001002004020040200402004020040
8020420039166100435887225801081008000810080020500640132200202003920039997769990801202008003220080032200392003911802011009910010080000100081011151180160020036800001002004020040200402004020040
80204200391500000030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000102011151180160020036800001002004020040200402004020040
8020420039150000003025801081008000810080020500640132200202003920039997769990801202008003220080032200392003911802011009910010080000100090011151180160020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420051150001282258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000035020316332003680000102004020040200402004020040
8002420039150001282258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000135020416442003680000102004020040200402004020040
80024200391500012682258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000135020316342003680000102004020040200402004020040
8002420039150001261258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000005020416452003680000102004020040200402004020040
80024200391500026182258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000135020516532003680000102004020040200402004020040
8002420039150001282258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000135020316242003680000102004020040200402004020040
8002420039150001282258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000135020416442003680000102004020040200402004020040
8002420039150001240258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000135020516442003680000102004020040200402004020040
8002420039150001282258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000135020616532003680000102004020040200402004020040
8002420039150001261258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000135020416542003680000102004020040200402004020040