Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRINTZ (vector, 4S)

Test 1: uops

Code:

  frintz v0.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723061254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303723061254725100010001000398160030183037303724143289510001000100030373037111001100000373116112629100030383038303830383038
1004303723061254725100010001000398160030183037303724143289510001000100030373037111001100010073116112629100030383038303830383038
10043037231261254725100010001000398160030183037303724143289510001000100030373037111001100002282873116112629100030383038303830383038
1004303723061254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303722093254725100010001000398160030183037303724143289510001000100030373037111001100000373116112629100030383038303830383038
1004303723061254725100010001000398160030183037303724143289510001000100030373037111001100000373116112629100030383038303830383038
1004303722061254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303722082254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
100430372212103254725100010001000398160030183037303724143289510001000100030373037111001100010073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  frintz v0.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000120103295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000060000710011611296330100001003003830038300383003830038
10204300372250000120103295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000200000710011611296330100001003003830038300383003830038
1020430037225000012010329547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000021120000710011611296330100001003003830038300383003830038
10204300372250000120822954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000002356680000733011611296330100001003003830038300383003830038
10204300372250000120103295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000130000710001611296330100001003003830038300383003830038
102043003722500001207682954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000002760000710011611296330100001003003830038300383003830038
10204300372250000001032954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000003260000710011611296330100001003003830038300383003830038
10204300372250000120103295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000230000710011611296330100001003003830038300383003830038
10204300372250000120103295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000200000710011611296330100001003003830038300383003830038
10204300372250000210103295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000100000710011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225006129547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010233640216222962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010103640216222962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010269640216222962910000103003830038300383003830038
10024300372251053629547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010289640216222962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010270640216222962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010293640216222962910000103003830038300383003830038
1002430037224006129547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010233640216222962910000103003830038300383003830038
1002430037225009629547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010302779640216222962910000103003830038300813003830038
1002430037225008229547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010269640216222962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010256640216222962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  frintz v0.4s, v8.4s
  frintz v1.4s, v8.4s
  frintz v2.4s, v8.4s
  frintz v3.4s, v8.4s
  frintz v4.4s, v8.4s
  frintz v5.4s, v8.4s
  frintz v6.4s, v8.4s
  frintz v7.4s, v8.4s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005815000001207225801081008000810080020500640132120020200392003999776999080120200800322008003220039202451180201100991001008000010001030111511801600200360800001002004020040200402004020040
802042003915010001207225801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000030111511801600200360800001002004020040200402004020040
802042003915000001207225801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000000111511801600200360800001002004020040200402004020040
802042003915000001207225801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010001000111511801600200360800001002004020040200402004020040
802042003915000001207225801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010001030111511801600200360800001002004020040200402004020040
80204200391500000007225801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000030111511801600200360800001002004020040200402004020040
802042003915000001203025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010001030111511801600200360800001002004020040200402004020040
80204200391500000007225801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010001030111511801600200360800001002004020040200402004020040
802042003915000001207225801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010001030111511801600200360800001002004020040200402004020040
802042003915000001207225801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010001030111511801600200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039150001052580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100000005020516432003680000102004020040200402004020040
800242003915000402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100000005020516442003680000102004020040200402004020040
800242003915000402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100000005020416342003680000102004020040200402004020040
80024200391500011092580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100000005020416442003680000102004020040200402004020040
8002420039150004202580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100000005020516442003680000102004020040200402004020040
800242003915000402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100000005020416442003680000102004020040200402004020040
800242003915000402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100000005020316342003680000102004020040200402004020040
800242003915000402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100000005020416442003680000102004020040200402004020040
800242003915000402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100000005020416442003680000102004020040200402004020040
800242003915000402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100000005020516442003680000102004020040200402004020040