Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRINTZ (vector, 8H)

Test 1: uops

Code:

  frintz v0.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372200061254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303722002482254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
100430372300061254725100010001000398160030183037303724143289510001000100030373037111001100000373116112701100030383038303830383038
1004303723001261254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
100430372300061254725100010001000398160130183037303724143289510001000100030373037111001100001073116112629100030383038303830383038
100430372300061254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
100430372300061254725100010001000398160130183037303724143289510001000100030373037111001100001073116112629100030383038303830383038
1004303722000103254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
100430372300082254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
100430372300061254725100010001000398160030183037303724143289510001000100030373037111001100000373116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  frintz v0.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000000168295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000003000071011611296330100001003003830038300383008530038
102043003722500000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000003000071011611296330100001003003830038300383003830038
102043003722500000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000200000000071011611296330100001003003830038300383003830038
102043003722500000261295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000000000071031611296330100001003008530085300383003830038
1020430037225000000168295472510100100100001001000050042771601300183003730037282643287451010020210000200100003003730037111020110099100100100001000000300000071011611296330100001003003830038300383003830228
1020430037225000120061295472510100100100001001000050042771601300183003730037282643287451010021010000200100003003730037111020110099100100100001000000000000071011611296330100001003003830038300383003830038
10204300372250002100103295472510100100100001001000050042771600300183003730037282643287451010020010000200100003013330037111020110099100100100001000000003000071011611296330100001003003830038300383003830038
102043003722500000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000000000071011611296330100001003003830038300383003830038
102043003722500000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000000000071011611296330100001003003830038300383003830038
102043003722400000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000000000071011611297050100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722512612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010010640216222962910000103003830038300383003830038
1002430037225121032954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010013640216222962910000103003830038300383003830038
10024300372250612954725100101010000101000050427716003001830037300372828672876710162201000020100003003730037111002110910101000010013640216222962910000103003830038300383003830038
1002430037225127682954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010013640216222962910000103003830038300383003830038
1002430037225121032954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010010640216222962910000103003830038300383003830038
100243003722501032954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010003640216222962910000103003830038300383003830038
1002430037225121032954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010013640216222962910000103003830038300383003830038
1002430037225121032954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010013640216222962910000103003830038300383003830038
1002430037225121032954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037225121032954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010003640216222962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  frintz v0.8h, v8.8h
  frintz v1.8h, v8.8h
  frintz v2.8h, v8.8h
  frintz v3.8h, v8.8h
  frintz v4.8h, v8.8h
  frintz v5.8h, v8.8h
  frintz v6.8h, v8.8h
  frintz v7.8h, v8.8h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)dde0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200581502227372580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001001031115118016020036800001002004020040200402004020040
802042003915012722580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001001001115118016020036800001002004020040200402004020040
80204200391500722580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000031115118016020036800001002004020040200402004020040
802042003915012722580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001001001115118016020036800001002004020040200402004020040
802042003915012722580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000031115118016020036800001002004020040200402004020040
8020420039150122422580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001001001115118016020036800001002004020040200402004020040
802042003915012722580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000017401115118016020036800001002004020040200402004020040
802042003915012302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001001031115118016020036800001002004020040200402004020040
80204200391500302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001001001115118016020036800001002004020040200402004020040
802042003915012512580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000001115118016020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242003915012822580010108000010800005064082002002020039200399996310019800102080000208000020039200391180021109101080000101035020216322003680000102004020040200402004020040
800242003915012402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000101005020316632003680000102004020040200402004020040
800242003915007262580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000101035020216332003680000102004020040200402004020040
800242003915012822580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000101035020216352003680000102004020040200402004020040
800242003915001262580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000101035020316232003680000102004020040200402004020040
800242003915012822580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100005020316322003680000102004020040200402004020040
800242003915012822580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000101005020616322003680000102004020040200402004020040
8002420039150012425800101080000108000050640000120020200392003910007310019800102080000208000020039200391180021109101080000100005020516762003680000102004020040200402004020040
80024200391500402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100005020316662003680000102004020040200402004020040
80024200391500402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100005020316322003680000102004020040200402004020040