Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRSQRTE (vector, 2D)

Test 1: uops

Code:

  frsqrte v0.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372206119002510001000100010445130183037303727383289510001000100030373037111001100000073116112919100030383038303830383038
100430372206119002510001000100010445130183037303727383289510001000100030373037111001100000073116112919100030383038303830383038
100430372306119002510001000100010445130183037303727383289510001000100030373037111001100000073116112919100030383038303830383038
100430372306119002510001000100010445130183037303727383289510001000100030373037111001100000073116112919100030383038303830383038
100430372306119002510001000100010445130183037303727383289510001000100030373037111001100020073116112919100030383038303830383038
100430372306119002510001000100010445130183037303727383289510001000100030373037111001100000073116112919100030383038303830383038
1004303723022919002510001000100010445130183037303727383289510001000100030373037111001100000073116112919100030383038303830383038
100430372306119002510001000100010445130183037303727383289510001000100030373037111001100000073116112919100030383038303830383038
100430372306119002510001000100010445130183037303727383289510001000100030373037111001100000073116112919100030383038303830383038
100430372266119002510001000100010445130183037303727383289510001000100030373037111001100000073116112919100030383038303830383038

Test 2: Latency 1->2

Code:

  frsqrte v0.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225002161199002510100100100001001000050010674650300183003730037285883287451010020010000200100003003730037111020110099100100100001000071011611299190100001003003830038300383003830038
1020430037225005161199002510100100100001251000050010674510300183003730037285883287451010020010000200100003003730037111020110099100100100001000071011611299190100001003003830038300383003830038
1020430037225003361199002510100100100001001000050010674511300183003730037285883287451010020010000200100003003730037111020110099100100100001000071011611299190100001003003830038300383003830038
1020430037225003661199002510100100100001001000050010674511300183003730037285883287451010020010000200100003003730037111020110099100100100001000071011611299190100001003003830038300383003830038
102043003722500361199002510100100100001001000050010674511300183003730037285883287451010020010000200100003003730037111020110099100100100001000071011611299190100001003003830038300383003830038
1020430037225002761199002510100100100001001000050010674511300183003730037285883287451010020010000200100003003730037111020110099100100100001000071011611299190100001003003830038300383003830038
1020430037225001861199002510100100100001001000050010674511300183003730037285883287451010020010000200100003003730037111020110099100100100001000071011611299190100001003003830038300383003830038
102043003722500061199002510100100100001001000050010674511300183003730037285883287451010020010000200100003003730037111020110099100100100001000071011622299190100001003003830038300383003830038
10204300372250012421199002510100100100001001000050010674511300183003730037285883287451010020010000200100003003730037111020110099100100100001000071011611299190100001003003830038300383003830038
1020430037224001561199002510100100100001001000050010674511300183003730037285883287451010020010000200100003003730037111020110099100100100001000071011611299190100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225001800611990025100101010000101000050106745113001830037300372861032876710010201000020100003003730037111002110910101000010000640316332991910000103003830038300383003830038
100243003722500000611990025100101010000101000050106745103001830037300372861032876710010201000020100003003730037111002110910101000010000640316332991910000103003830038300383003830038
100243003722500300611990025100101010000101000050106745113001830037300372861032876710010201000020100003003730037111002110910101000010000640316332991910000103003830038300383003830038
100243003722500000611990025100101010000101000050106745103001830037300372861032876710010201000020100003003730037111002110910101000010000640316332991910000103003830038300383003830038
10024300372250422800611990025100101010000101000050106745103001830037300372861032876710010201000020100593003730037111002110910101000010000640316332991910000103003830038300383003830038
100243003722500000611990025100101010000101000050106745103001830037300372861032876710010201000020100003003730037111002110910101000010000640316332999210000103003830038300383003830038
100243003722500000611990025100101010000101000050106745113001830037300372861032876710010201000020100003003730037111002110910101000010000640316332991910000103003830038300383003830038
100243003722500000611990025100101010000101000050106745113001830037300372861032876710010201000020100003003730037111002110910101000010000640316332991910000103003830038300383003830038
100243003722500000611990025100101010000101000050106745113001830037300372861032876710010201000020100003003730037111002110910101000010000640316332991910000103003830038300383003830038
1002430037225401500611990025100101010000101000050106745103001830037300372861032880010010201000020100003003730037111002110910101000010000640316332991910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  frsqrte v0.2d, v8.2d
  frsqrte v1.2d, v8.2d
  frsqrte v2.2d, v8.2d
  frsqrte v3.2d, v8.2d
  frsqrte v4.2d, v8.2d
  frsqrte v5.2d, v8.2d
  frsqrte v6.2d, v8.2d
  frsqrte v7.2d, v8.2d
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)fetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204800405990000392580100100800001008000050064000008002008003980039699716699938010020080008200800088003980088118020110099100100800001000011151170160800360800001008004080040800898004080040
80204800395990001392580100100800001008000050064000008002008003980039699716699938010020080008200800088003980039118020110099100100800001000011151170160800360800001008004080040800408004080040
80204800395990000392580100100800001008000050064000008002008003980039699716699938010020080008200800088003980039118020110099100100800001000011151170160800360800001008004080040800408004080040
80204800395990000392580100100800001008000050064000008002008003980039699716699938010020080008200800088003980039118020110099100100800001000011151170161800360800001008004080040800408004080040
80204800395990000392580100100800001008000050064000008002008003980039699716699938010020080008200800088003980039118020110099100100800001000011151170160800360800001008004080040800408004080040
802048003959900007292580100100800001138000050064000008002008003980039699716699938010020080008200800088003980039118020110099100100800001000011151170160800360800001008004080040800408004080040
80204800396000000392580100100800001008000050064000008002008003980039699716699938010020080008200800088003980039118020110099100100800001000011151170160800360800001008004080040800408004080040
80204800395990000392580100100800001008000050064000008002008003980039699716699938010020080008200800088003980039118020110099100100800001000011151170160800360800001008004080040800408004080040
802048003960000005142580100100800001008000050064000008002008003980039699716699938010020080008200800088003980039118020110099100100800001000011151170160800360800001008004080040800408004080040
80204800395990000392580100100800001008000050064000008002008003980039699716699938010020080008200800088003980039118020210099100100800001000011151170160800360800001008004080040800408004080040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acbranch mispred nonspec (cb)cdcfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800248004060000902580010108000010800005064000008002008003980039699863700198001020800002080000800398003911800211091010800001000000005020081610108003480000108004080040800408004080040
8002480039600002280258001010800001080000506400000800200800398003969986370019800102080000208000080039800391180021109101080000100000000502008167108003480000108004080040800408004080040
8002480039599001101258001010800001080000506400000800200800398003969986370019800102080000208000080039800391180021109101080000100000000502001016898003480000108004080040800408004080040
800248003959900502580010108000010800005064000008002008003980039699863700198001020800002080000800398003911800211091010800001000000005020081610108003480000108004080040800408004080040
800248003959900715258001010800001080000506400000800690800398003969986370019800102080000208000080039800391180021109101080000100000900502008161288003480000108004080040800408004080040
80024800396000071525800101080000108000050640000080020080039800396998637001980010208000020800008003980039118002110910108000010000000050200101610108003480000108004080040800408004080040
80024800396000050258001010800001080000506400000800200800398003969986370019800102080000208000080039800391180021109101080000100000000502006168108003480000108004080040800408004080040
80024800396000050258001010800001080000506400000800200800398003969986370019800102080000208000080039800391180021109101080000100020000502007329108003480000108004080040800408004080040
80024800395990351715258001010800001080000506400000800200800398003969986370019800102080000208000080039800391180021109101080000100000000502006167108003480000108004080040800408004080040
8002480039599009225800271080000108000050640000080020080039800396998677009380010208000020800408003980088118002110910108000010021260050200816988003480000108004080040800408004080040