Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
frsqrte v0.2d, v0.2d
movi v0.16b, 1 movi v1.16b, 2
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 0.000
Load/store unit issues: 0.000
SIMD/FP unit issues: 1.000
| retire uop (01) | cycle (02) | 03 | 1e | 3f | 4e | 51 | schedule uop (52) | schedule simd uop (54) | dispatch simd uop (57) | ldst uops in schedulers (5b) | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map simd uop (7e) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd alu (9a) | l1d tlb miss (a1) | l1d cache writeback (a8) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? simd retires (ee) | f5 | f6 | f7 | f8 | fd |
| 1004 | 3037 | 22 | 0 | 61 | 1900 | 25 | 1000 | 1000 | 1000 | 104451 | 3018 | 3037 | 3037 | 2738 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 2919 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
| 1004 | 3037 | 22 | 0 | 61 | 1900 | 25 | 1000 | 1000 | 1000 | 104451 | 3018 | 3037 | 3037 | 2738 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 2919 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
| 1004 | 3037 | 23 | 0 | 61 | 1900 | 25 | 1000 | 1000 | 1000 | 104451 | 3018 | 3037 | 3037 | 2738 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 2919 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
| 1004 | 3037 | 23 | 0 | 61 | 1900 | 25 | 1000 | 1000 | 1000 | 104451 | 3018 | 3037 | 3037 | 2738 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 2919 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
| 1004 | 3037 | 23 | 0 | 61 | 1900 | 25 | 1000 | 1000 | 1000 | 104451 | 3018 | 3037 | 3037 | 2738 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 2 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 2919 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
| 1004 | 3037 | 23 | 0 | 61 | 1900 | 25 | 1000 | 1000 | 1000 | 104451 | 3018 | 3037 | 3037 | 2738 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 2919 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
| 1004 | 3037 | 23 | 0 | 229 | 1900 | 25 | 1000 | 1000 | 1000 | 104451 | 3018 | 3037 | 3037 | 2738 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 2919 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
| 1004 | 3037 | 23 | 0 | 61 | 1900 | 25 | 1000 | 1000 | 1000 | 104451 | 3018 | 3037 | 3037 | 2738 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 2919 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
| 1004 | 3037 | 23 | 0 | 61 | 1900 | 25 | 1000 | 1000 | 1000 | 104451 | 3018 | 3037 | 3037 | 2738 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 2919 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
| 1004 | 3037 | 22 | 6 | 61 | 1900 | 25 | 1000 | 1000 | 1000 | 104451 | 3018 | 3037 | 3037 | 2738 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 2919 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
Code:
frsqrte v0.2d, v0.2d
movi v0.16b, 1 movi v1.16b, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 3.0037
| retire uop (01) | cycle (02) | 03 | 18 | 19 | 1e | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d cache writeback (a8) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10204 | 30037 | 225 | 0 | 0 | 21 | 61 | 19900 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 1067465 | 0 | 30018 | 30037 | 30037 | 28588 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29919 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10204 | 30037 | 225 | 0 | 0 | 51 | 61 | 19900 | 25 | 10100 | 100 | 10000 | 125 | 10000 | 500 | 1067451 | 0 | 30018 | 30037 | 30037 | 28588 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29919 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10204 | 30037 | 225 | 0 | 0 | 33 | 61 | 19900 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 1067451 | 1 | 30018 | 30037 | 30037 | 28588 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29919 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10204 | 30037 | 225 | 0 | 0 | 36 | 61 | 19900 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 1067451 | 1 | 30018 | 30037 | 30037 | 28588 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29919 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10204 | 30037 | 225 | 0 | 0 | 3 | 61 | 19900 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 1067451 | 1 | 30018 | 30037 | 30037 | 28588 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29919 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10204 | 30037 | 225 | 0 | 0 | 27 | 61 | 19900 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 1067451 | 1 | 30018 | 30037 | 30037 | 28588 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29919 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10204 | 30037 | 225 | 0 | 0 | 18 | 61 | 19900 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 1067451 | 1 | 30018 | 30037 | 30037 | 28588 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29919 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10204 | 30037 | 225 | 0 | 0 | 0 | 61 | 19900 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 1067451 | 1 | 30018 | 30037 | 30037 | 28588 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 2 | 2 | 29919 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10204 | 30037 | 225 | 0 | 0 | 12 | 421 | 19900 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 1067451 | 1 | 30018 | 30037 | 30037 | 28588 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29919 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10204 | 30037 | 224 | 0 | 0 | 15 | 61 | 19900 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 1067451 | 1 | 30018 | 30037 | 30037 | 28588 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29919 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
Result (median cycles for code): 3.0037
| retire uop (01) | cycle (02) | 03 | 18 | 19 | 1e | 1f | 3a | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d cache writeback (a8) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10024 | 30037 | 225 | 0 | 0 | 18 | 0 | 0 | 61 | 19900 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 1067451 | 1 | 30018 | 30037 | 30037 | 28610 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 10000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 29919 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 61 | 19900 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 1067451 | 0 | 30018 | 30037 | 30037 | 28610 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 10000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 29919 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10024 | 30037 | 225 | 0 | 0 | 3 | 0 | 0 | 61 | 19900 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 1067451 | 1 | 30018 | 30037 | 30037 | 28610 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 10000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 29919 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 61 | 19900 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 1067451 | 0 | 30018 | 30037 | 30037 | 28610 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 10000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 29919 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10024 | 30037 | 225 | 0 | 4 | 228 | 0 | 0 | 61 | 19900 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 1067451 | 0 | 30018 | 30037 | 30037 | 28610 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 10059 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 29919 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 61 | 19900 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 1067451 | 0 | 30018 | 30037 | 30037 | 28610 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 10000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 29992 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 61 | 19900 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 1067451 | 1 | 30018 | 30037 | 30037 | 28610 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 10000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 29919 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 61 | 19900 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 1067451 | 1 | 30018 | 30037 | 30037 | 28610 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 10000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 29919 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 61 | 19900 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 1067451 | 1 | 30018 | 30037 | 30037 | 28610 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 10000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 29919 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10024 | 30037 | 225 | 4 | 0 | 15 | 0 | 0 | 61 | 19900 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 1067451 | 0 | 30018 | 30037 | 30037 | 28610 | 3 | 28800 | 10010 | 20 | 10000 | 20 | 10000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 29919 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
Count: 8
Code:
frsqrte v0.2d, v8.2d frsqrte v1.2d, v8.2d frsqrte v2.2d, v8.2d frsqrte v3.2d, v8.2d frsqrte v4.2d, v8.2d frsqrte v5.2d, v8.2d frsqrte v6.2d, v8.2d frsqrte v7.2d, v8.2d
movi v8.16b, 9
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0005
| retire uop (01) | cycle (02) | 03 | 19 | 1e | 1f | 3a | 3f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d cache writeback (a8) | ac | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | fetch restart (de) | e0 | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80204 | 80040 | 599 | 0 | 0 | 0 | 0 | 39 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 0 | 80020 | 0 | 80039 | 80039 | 69971 | 6 | 69993 | 80100 | 200 | 80008 | 200 | 80008 | 80039 | 80088 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 1 | 1 | 1 | 5117 | 0 | 16 | 0 | 80036 | 0 | 80000 | 100 | 80040 | 80040 | 80089 | 80040 | 80040 |
| 80204 | 80039 | 599 | 0 | 0 | 0 | 1 | 39 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 0 | 80020 | 0 | 80039 | 80039 | 69971 | 6 | 69993 | 80100 | 200 | 80008 | 200 | 80008 | 80039 | 80039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 1 | 1 | 1 | 5117 | 0 | 16 | 0 | 80036 | 0 | 80000 | 100 | 80040 | 80040 | 80040 | 80040 | 80040 |
| 80204 | 80039 | 599 | 0 | 0 | 0 | 0 | 39 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 0 | 80020 | 0 | 80039 | 80039 | 69971 | 6 | 69993 | 80100 | 200 | 80008 | 200 | 80008 | 80039 | 80039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 1 | 1 | 1 | 5117 | 0 | 16 | 0 | 80036 | 0 | 80000 | 100 | 80040 | 80040 | 80040 | 80040 | 80040 |
| 80204 | 80039 | 599 | 0 | 0 | 0 | 0 | 39 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 0 | 80020 | 0 | 80039 | 80039 | 69971 | 6 | 69993 | 80100 | 200 | 80008 | 200 | 80008 | 80039 | 80039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 1 | 1 | 1 | 5117 | 0 | 16 | 1 | 80036 | 0 | 80000 | 100 | 80040 | 80040 | 80040 | 80040 | 80040 |
| 80204 | 80039 | 599 | 0 | 0 | 0 | 0 | 39 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 0 | 80020 | 0 | 80039 | 80039 | 69971 | 6 | 69993 | 80100 | 200 | 80008 | 200 | 80008 | 80039 | 80039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 1 | 1 | 1 | 5117 | 0 | 16 | 0 | 80036 | 0 | 80000 | 100 | 80040 | 80040 | 80040 | 80040 | 80040 |
| 80204 | 80039 | 599 | 0 | 0 | 0 | 0 | 729 | 25 | 80100 | 100 | 80000 | 113 | 80000 | 500 | 640000 | 0 | 80020 | 0 | 80039 | 80039 | 69971 | 6 | 69993 | 80100 | 200 | 80008 | 200 | 80008 | 80039 | 80039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 1 | 1 | 1 | 5117 | 0 | 16 | 0 | 80036 | 0 | 80000 | 100 | 80040 | 80040 | 80040 | 80040 | 80040 |
| 80204 | 80039 | 600 | 0 | 0 | 0 | 0 | 39 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 0 | 80020 | 0 | 80039 | 80039 | 69971 | 6 | 69993 | 80100 | 200 | 80008 | 200 | 80008 | 80039 | 80039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 1 | 1 | 1 | 5117 | 0 | 16 | 0 | 80036 | 0 | 80000 | 100 | 80040 | 80040 | 80040 | 80040 | 80040 |
| 80204 | 80039 | 599 | 0 | 0 | 0 | 0 | 39 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 0 | 80020 | 0 | 80039 | 80039 | 69971 | 6 | 69993 | 80100 | 200 | 80008 | 200 | 80008 | 80039 | 80039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 1 | 1 | 1 | 5117 | 0 | 16 | 0 | 80036 | 0 | 80000 | 100 | 80040 | 80040 | 80040 | 80040 | 80040 |
| 80204 | 80039 | 600 | 0 | 0 | 0 | 0 | 514 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 0 | 80020 | 0 | 80039 | 80039 | 69971 | 6 | 69993 | 80100 | 200 | 80008 | 200 | 80008 | 80039 | 80039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 1 | 1 | 1 | 5117 | 0 | 16 | 0 | 80036 | 0 | 80000 | 100 | 80040 | 80040 | 80040 | 80040 | 80040 |
| 80204 | 80039 | 599 | 0 | 0 | 0 | 0 | 39 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 0 | 80020 | 0 | 80039 | 80039 | 69971 | 6 | 69993 | 80100 | 200 | 80008 | 200 | 80008 | 80039 | 80039 | 1 | 1 | 80202 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 1 | 1 | 1 | 5117 | 0 | 16 | 0 | 80036 | 0 | 80000 | 100 | 80040 | 80040 | 80040 | 80040 | 80040 |
Result (median cycles for code divided by count): 1.0005
| retire uop (01) | cycle (02) | 03 | l2 tlb miss data (0b) | 1e | 3f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache writeback (a8) | a9 | ac | branch mispred nonspec (cb) | cd | cf | l1i cache miss demand (d3) | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80024 | 80040 | 600 | 0 | 0 | 90 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 80020 | 0 | 80039 | 80039 | 69986 | 3 | 70019 | 80010 | 20 | 80000 | 20 | 80000 | 80039 | 80039 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5020 | 0 | 8 | 16 | 10 | 10 | 80034 | 80000 | 10 | 80040 | 80040 | 80040 | 80040 | 80040 |
| 80024 | 80039 | 600 | 0 | 0 | 2280 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 80020 | 0 | 80039 | 80039 | 69986 | 3 | 70019 | 80010 | 20 | 80000 | 20 | 80000 | 80039 | 80039 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5020 | 0 | 8 | 16 | 7 | 10 | 80034 | 80000 | 10 | 80040 | 80040 | 80040 | 80040 | 80040 |
| 80024 | 80039 | 599 | 0 | 0 | 1101 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 80020 | 0 | 80039 | 80039 | 69986 | 3 | 70019 | 80010 | 20 | 80000 | 20 | 80000 | 80039 | 80039 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5020 | 0 | 10 | 16 | 8 | 9 | 80034 | 80000 | 10 | 80040 | 80040 | 80040 | 80040 | 80040 |
| 80024 | 80039 | 599 | 0 | 0 | 50 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 80020 | 0 | 80039 | 80039 | 69986 | 3 | 70019 | 80010 | 20 | 80000 | 20 | 80000 | 80039 | 80039 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5020 | 0 | 8 | 16 | 10 | 10 | 80034 | 80000 | 10 | 80040 | 80040 | 80040 | 80040 | 80040 |
| 80024 | 80039 | 599 | 0 | 0 | 715 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 80069 | 0 | 80039 | 80039 | 69986 | 3 | 70019 | 80010 | 20 | 80000 | 20 | 80000 | 80039 | 80039 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 5020 | 0 | 8 | 16 | 12 | 8 | 80034 | 80000 | 10 | 80040 | 80040 | 80040 | 80040 | 80040 |
| 80024 | 80039 | 600 | 0 | 0 | 715 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 80020 | 0 | 80039 | 80039 | 69986 | 3 | 70019 | 80010 | 20 | 80000 | 20 | 80000 | 80039 | 80039 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5020 | 0 | 10 | 16 | 10 | 10 | 80034 | 80000 | 10 | 80040 | 80040 | 80040 | 80040 | 80040 |
| 80024 | 80039 | 600 | 0 | 0 | 50 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 80020 | 0 | 80039 | 80039 | 69986 | 3 | 70019 | 80010 | 20 | 80000 | 20 | 80000 | 80039 | 80039 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5020 | 0 | 6 | 16 | 8 | 10 | 80034 | 80000 | 10 | 80040 | 80040 | 80040 | 80040 | 80040 |
| 80024 | 80039 | 600 | 0 | 0 | 50 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 80020 | 0 | 80039 | 80039 | 69986 | 3 | 70019 | 80010 | 20 | 80000 | 20 | 80000 | 80039 | 80039 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 5020 | 0 | 7 | 32 | 9 | 10 | 80034 | 80000 | 10 | 80040 | 80040 | 80040 | 80040 | 80040 |
| 80024 | 80039 | 599 | 0 | 351 | 715 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 80020 | 0 | 80039 | 80039 | 69986 | 3 | 70019 | 80010 | 20 | 80000 | 20 | 80000 | 80039 | 80039 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5020 | 0 | 6 | 16 | 7 | 10 | 80034 | 80000 | 10 | 80040 | 80040 | 80040 | 80040 | 80040 |
| 80024 | 80039 | 599 | 0 | 0 | 92 | 25 | 80027 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 80020 | 0 | 80039 | 80039 | 69986 | 7 | 70093 | 80010 | 20 | 80000 | 20 | 80040 | 80039 | 80088 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 2 | 1 | 2 | 6 | 0 | 0 | 5020 | 0 | 8 | 16 | 9 | 8 | 80034 | 80000 | 10 | 80040 | 80040 | 80040 | 80040 | 80040 |