Firestorm: FRSQRTE (vector, 2S) measurements

Code:

  frsqrte v0.2s, v0.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	22	15	61	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038
1004	3037	23	90	61	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	3	3	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	1	0	73	1	16	1	1	2918	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038
1004	3037	23	18	61	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	1900	25	1000	1000	1042	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	18	0	75	1	16	1	1	2919	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->2

Code:

  frsqrte v0.2s, v0.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	156	19900	25	10100	100	10000	100	10000	500	1067451	0	30018	30037	30037	28588	3	28745	10168	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	0	0	0	710	1	16	1	1	29919	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	19900	25	10100	100	10000	100	10000	500	1067451	0	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30084	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29919	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	19900	25	10100	100	10000	100	10000	500	1067451	0	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29919	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	19900	25	10100	100	10000	100	10000	500	1067451	1	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29919	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	82	19852	25	10100	102	10000	100	10042	610	1067451	0	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	0	0	0	710	1	16	1	1	29919	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	251	19900	25	10100	100	10000	100	10000	500	1067451	0	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29919	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	19900	25	10100	100	10000	100	10000	500	1067451	1	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	2	1	2	1283	0	742	1	16	2	1	29919	10000	100	30038	30038	30085	30038	30038
10204	30037	225	0	103	19900	25	10100	100	10000	100	10000	500	1067451	0	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	0	0	0	710	1	16	1	1	29919	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	19900	25	10100	100	10000	100	10000	500	1067451	0	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29919	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	19900	25	10100	100	10000	100	10000	500	1067451	1	30162	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	0	0	0	710	1	16	1	1	29919	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	224	0	0	0	0	61	19900	25	10010	10	10000	10	10000	50	1067451	0	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	29919	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	19900	25	10010	10	10000	10	10000	50	1067451	0	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	29919	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	61	19900	25	10010	10	10000	10	10000	50	1067451	1	30018	30037	30037	28610	3	28767	10010	20	10000	20	10068	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	29919	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	19900	25	10010	10	10000	10	10000	50	1067451	1	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	29919	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	19900	25	10010	10	10000	10	10000	50	1067451	0	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	29919	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	19900	25	10010	10	10000	10	10000	50	1067451	1	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	29919	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	19900	25	10010	10	10000	10	10000	50	1067451	1	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	29919	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	19900	25	10010	10	10000	10	10000	50	1067451	0	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	29919	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	19900	25	10010	10	10000	10	10000	50	1067451	0	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	29919	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	19900	25	10010	10	10000	10	10000	50	1067451	0	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	29919	10000	10	30038	30038	30038	30038	30038

Test 3: throughput

Count: 8

Code:

  frsqrte v0.2s, v8.2s
  frsqrte v1.2s, v8.2s
  frsqrte v2.2s, v8.2s
  frsqrte v3.2s, v8.2s
  frsqrte v4.2s, v8.2s
  frsqrte v5.2s, v8.2s
  frsqrte v6.2s, v8.2s
  frsqrte v7.2s, v8.2s

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80205	80040	599	9	0	39	25	80100	100	80000	100	80000	500	640000	0	80020	80136	80039	69971	0	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5117	0	16	0	80036	80000	100	80040	80040	80040	80040	80040
80204	80039	600	0	0	39	25	80100	100	80000	100	80000	500	640000	0	80020	80039	80039	69971	0	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5117	0	16	0	80036	80000	100	80040	80040	80040	80040	80040
80204	80039	600	0	0	324	25	80100	100	80000	100	80000	500	640000	1	80020	80039	80039	69971	0	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5117	0	16	0	80036	80000	100	80040	80040	80040	80040	80040
80204	80039	599	0	0	725	25	80100	100	80000	100	80000	500	640000	0	80020	80039	80039	69971	0	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5117	0	16	0	80036	80000	100	80040	80040	80040	80040	80040
80204	80039	599	0	0	704	25	80100	100	80000	100	80000	500	640000	0	80020	80039	80039	69971	0	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5117	0	16	0	80036	80000	100	80040	80040	80040	80040	80040
80204	80039	599	0	0	704	25	80100	100	80000	100	80000	500	640000	0	80020	80039	80039	69971	0	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5117	0	16	0	80036	80000	100	80040	80040	80040	80040	80040
80204	80039	599	0	0	39	25	80100	100	80000	100	80000	500	640000	0	80020	80039	80039	69971	0	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5117	0	16	0	80036	80000	100	80040	80040	80040	80040	80040
80204	80039	600	0	0	704	25	80100	100	80000	100	80000	500	640000	0	80020	80039	80039	69971	0	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5117	0	16	0	80036	80000	100	80040	80040	80040	80040	80040
80204	80039	599	0	0	39	25	80100	100	80000	100	80000	500	640000	0	80020	80039	80039	69971	0	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5117	0	16	0	80036	80000	100	80040	80040	80040	80040	80040
80204	80039	600	0	0	39	25	80100	100	80000	100	80000	500	640000	0	80020	80039	80039	69971	0	6	70024	80126	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	6	1	1	1	5117	0	16	0	80036	80000	100	80040	80040	80040	80040	80040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	18	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	80039	600	0	2	0	0	0	50	25	80010	10	80000	10	80000	50	640000	0	1	5	80020	80039	80039	69986	0	3	70019	80010	20	80000	20	80000	80089	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	0	0	22	16	9	6	80034	0	80000	10	80040	80040	80040	80089	80040
80024	80039	599	0	0	0	12	0	92	25	80010	10	80000	10	80000	50	640000	0	0	0	80020	80039	80039	69986	0	3	70019	80062	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	2368	0	5020	0	0	14	56	10	5	80185	0	80000	10	80040	80040	80040	80040	80040
80024	80039	599	1	0	1	174	108	715	100	80058	10	80024	10	80078	50	640203	0	0	0	80020	80039	80039	70005	0	17	70202	80088	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	2	0	0	5020	5	2	9	32	8	10	80034	0	80000	10	80040	80040	80040	80040	80040
80024	80039	599	0	0	0	0	0	757	25	80010	10	80000	10	80000	50	640000	0	0	0	80020	80039	80039	69986	0	3	70019	80010	20	80110	20	80041	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	5	0	15	16	11	8	80034	0	80000	10	80040	80040	80040	80040	80040
80024	80039	599	0	0	0	0	0	715	25	80010	10	80000	10	80000	50	640000	0	0	0	80020	80039	80039	69986	0	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	0	0	12	16	4	8	80034	0	80000	10	80040	80040	80040	80040	80040
80024	80039	599	0	0	0	0	0	715	25	80010	10	80000	10	80000	50	640000	0	1	0	80020	80039	80039	69986	0	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	0	0	5	16	7	5	80034	0	80000	10	80040	80040	80040	80040	80040
80024	80039	599	0	0	0	0	0	715	25	80010	10	80000	10	80000	50	640000	0	0	0	80020	80039	80039	69986	0	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	5	2	8	16	8	8	80034	0	80000	10	80040	80040	80040	80040	80040
80024	80039	599	0	0	0	0	0	50	25	80010	10	80000	10	80000	50	640000	0	0	0	80020	80039	80039	69986	0	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	0	0	8	16	7	4	80034	0	80000	10	80040	80040	80040	80040	80040
80024	80039	599	0	0	0	0	0	50	25	80010	10	80000	10	80000	50	640000	0	0	0	80020	80039	80039	69986	0	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	5	2	8	16	9	8	80034	0	80000	10	80040	80089	80040	80040	80087
80024	80039	600	0	0	0	0	0	50	25	80010	10	80000	10	80000	50	640000	0	0	0	80020	80039	80039	69986	0	3	70019	80010	20	80000	20	80000	80088	80039	1	1	80021	10	9	10	10	80000	10	0	15	0	5020	0	0	6	16	6	10	80034	0	80000	10	80040	80040	80040	80040	80040

FRSQRTE (vector, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations