Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRSQRTS (vector, 4H)

Test 1: uops

Code:

  frsqrts v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004403730061340725100010001000531908140184037403732583389510001000200040374037111001100009073116113473100040384038403840384038
1004403730061340725100010001000531908140184037403732583389510001000200040374037111001100002173116113473100040384038403840384038
1004403731061340725100010001000531908040184037403732583389510001000200040374037111001100001873116113473100040384038403840384038
1004403730961340725100010001000531908040184037407332583389510001000200040374037111001100009673116113473100040384038403840384038
1004403730061340725100010001000531908040184037403732583389510001000200040374037111001100003673116113473100040384038403840384038
1004403730061340725100010001000531908040184037403732583389510001000200040374037111001100008173116113473100040384038403840384038
100440373106134072510001000100053190814018403740373258338951000100020004037403711100110000073116113473100040384038403840384038
100440373106134072510001000100053190804018403740373258338951000100020004037403711100110000073116113473100040384038403840384038
100440373008234072510001000100053190804018403740373258338951000100020004037403711100110000073116113473100040384038403840384038
100440373006134072510001000100053190804018403740373258338951000100020004037403711100110000073116113473100040384038403840384038

Test 2: Latency 1->2

Code:

  frsqrts v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03l1i tlb fill (04)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102044003730010613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
102044003730000613940725101001001000010010000500570690814001840037400373810833874510100200100002002000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
102044003729909613940725101001001000010010000500570690814001840037400373810833874510100200100002002000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
1020440037299006139407251010010010000100100005005706908140018400374003738108338745101002001000020020000400374003711102011009910010010000100000710116113947924100001004003840038400384003840038
102044008430000613940725101001001000010010000500570690814001840037400373810833874510100200100002002000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
102044003730000613940725101001001000010010000500570690814001840037400373810833874510100200100002002000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
102044003729900613940725101001001000010010000500570690814001840037400373810833874510100200100002002000040037400371110202100991001001000010000071011611394790100001004003840038400384003840038
102044003729900613940725101001001000010010000500570690814001840037400373810833874510100200100002002000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
102044003729900613940725101001001000010010000500570690814001840037400373810833874510100200100002002000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
102044003730000823940725101001001000010010000500570690814001840037400373810833874510100200100002002000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024400372990414613940725100101010000101000050570690804001840037400373813333884210010201000020200004003740037111002110910101000010010640316333947310000104003840038400384003840038
100244003730000613940725100101010000101000050570690804001840037400373813033876710010201000020200004003740037111002110910101000010000640316333947310000104003840038400384003840038
100244003730000613940725100101010000101000050570690804001840037400373813033876710010201000020200004003740037111002110910101000010000640316333947310000104003840038400384003840038
100244003730000613940725100101010000101000050570690804001840037400373813033876710010201000020200004003740037111002110910101000010000640316333947310000104003840038400384003840038
100244003729900613940725100101010000101000050570690804001840037400373813083878710010201000020200004003740037111002110910101000010000640316333947310000104003840038400384003840038
100244003730000613940725100101010000101000050570690804001840037400373813033876710010201000020200004003740037111002110910101000010000640316333947310000104003840038400384003840038
100244003730000613940725100101010000101000050570690814001840037400373813033876710010201000020200004003740037111002110910101000010000640316333947310000104003840038400384003840038
100244003730000613940725100101010000101000050570690804001840037400373813033876710010201000020200004003740037111002110910101000010000640316333947310000104003840038400384003840038
100244003729900613940725100101010000101000050570690814001840037400373813033876710010201000020200004003740037111002110910101000010000640316333947310000104003840038400384003840038
100244003730000613940725100101010000101000050570970004001840037400373813033876710606201000020200004003740037111002110910101000010239640316333947310000104003840038400384003840038

Test 3: Latency 1->3

Code:

  frsqrts v0.4h, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020440037299000061394072510100100100001001000050057069081940018400374003738108338745101002001000020020000400374003711102011009910010010000100000000710911611394790100001004003840181400384003840038
1020440037299000061394072510100100100001001000050057069081940018400374003738108338745101002001000020020000400374003711102011009910010010000100000000710911611394790100001004003840038400384003840038
10204400372990000156394072510100100100001001000050057069080940018400374003738108338745101002001000020020000400374003711102011009910010010000100000000710911611394790100001004003840038400384003840038
1020440037300000061394072510100100100001001000050057069080940018400374003738108338745101002001000020020000400374003711102011009910010010000100000000710911611394790100001004003840038400384003840038
1020440037301000061394072510100100100001001000050057069081040018400374003738108338745101002001000020020000400374003711102011009910010010000100000790710911611394790100001004003840038400384003840038
1020440037300000061394072510100100100001001000050057069081040018400374003738108338745101002001000020020000400374003711102011009910010010000100000000710911611394790100001004003840180400384003840038
102044003730000015912394072510100100100001001000050057069080940018400374003738108338745101002001000020020000400374003711102011009910010010000100000000710911611394790100001004003840038400384003840038
1020440037299000061394072510100100100001001000050057069081940018400374003738108338745101002001000020020000400374003711102011009910010010000100000000710911611394790100001004003840038400384003840038
1020440037299000061394072510100100100001001000050057069081040018400374003738108338745101002001000020020000400374003711102011009910010010000100000000710911611394790100001004003840038400384003840038
1020440037301000061394072510100100100001001000050057069081940018400374003738108338745101002001000020020000400374003711102011009910010010000100033000710911611394790100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024400373000000613940725100101010000101000050570690814001840037400373813033876710010201000020200004003740037111002110910101000010000006405162239473010000104003840038400384003840038
10024400372990000613940725100101010000101000050570690804001840037400373813033876710010201000020200004003740037111002110910101000010000006402162239473010000104003840038400384003840038
10024400373000010613940725100101010000101000050570690814001840037400373813033876710010201000020200004003740037111002110910101000010000006402162239473010000104003840038400384003840038
10024400373000000613940725100101010000101000050570690804001840037400373813033876710010201000020200004003740037111002110910101000010000006402162239473010000104003840038400384003840038
100244008430000033613940725100101010000101000050570690804001840037400373813033876710010201000020200004003740037211002110910101000010000006402162239473010000104003840038400384003840038
10024400373000000613940725100101010000101000050570690804001840037400373813033876710010201000020200004003740037111002110910101000010000006402162239473010000104003840038400384003840038
10024400373000000613940725100101010000101000050570690804001840037400373813033876710010201000020200004003740037111002110910101000010000006402162239473010000104003840038400384003840038
10024400373000000613940725100101010000101000050570690804001840037400373813033876710010201000020200004003740037111002110910101000010000006402162239473210000104003840038400384003840086
10024400373000100823940725100101010006101014850570690804001840037400373813033876710010201000020200004003740037111002110910101000010000006402162239473010000104003840038400384003840038
10024400373000000613940725100101010000101000050570690804001840037400373813033876710010201000020200004003740037111002110910101000010000006402162239473010000104003840038400384003840038

Test 4: throughput

Count: 8

Code:

  frsqrts v0.4h, v8.4h, v9.4h
  frsqrts v1.4h, v8.4h, v9.4h
  frsqrts v2.4h, v8.4h, v9.4h
  frsqrts v3.4h, v8.4h, v9.4h
  frsqrts v4.4h, v8.4h, v9.4h
  frsqrts v5.4h, v8.4h, v9.4h
  frsqrts v6.4h, v8.4h, v9.4h
  frsqrts v7.4h, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03091e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005815000422580100100800001008000050064000020021200402004099733999880100200800002001600002004020040118020110099100100800001003005110041633200370800001002004120041200412004120041
802042004015000422580100100800001008000050064000020021200402004099733999880100200800002001600002004020040118020110099100100800001000005110031633200370800001002004120041200412004120041
802042004015000422580100100800001008000050064000020021200402004099733999880100200800002001600002004020040118020110099100100800001000005110031623200370800001002024620041200412004120041
8020420040150003982580100100800001008000050064000020021200402004099733999880100200800002001602142004020040118020110099100100800001000005110021632200370800001002004120041200412004120041
802042004015000422580100100800001008000050064000020021200402004099733999880100200800002001600002004020040118020110099100100800001000005110031632200370800001002004120041200412004120041
802042004015000422580100100800001008000050064000020021200402004099733999880100200800002001600002004020040118020110099100100800001000005110031633200370800001002004120041200412004120041
802042004015000422580100100800001008000050064000020021200402004099733999880100200800002001600002004020040118020110099100100800001000005110021633200370800001002004120041200412004120041
802042004015000422580100100800001008000050064000020021200402004099923999880100200800002001600002004020040118020110099100100800001001005110021623200370800001002004120099200412004120041
8020420040150012422580100100800001008000050064000020021200402004099733999880100200800002001600002004020040118020110099100100800001000005110021633200370800001002004120041200412004120041
802042004015000422580100100800001008000050064000020021200402004099733999880100200800002001600002004020040118020110099100100800001000005110031633200370800001002004120041200412004120041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd0d5map dispatch bubble (d6)dbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200401500622580010108000010800005064000012002120040200409996031002080010208000020160000200402004011800211091010800001000050200416034200370080000102004120041200412004120041
80024200401500412580010108000010800005064000012002120040200409996031002080010208000020160000200402004011800211091010800001000050200416034200370080000102004120041200412004120041
80024200401500412580010108000010800005064000012002120040200409996031002080010208000020160000200402004011800211091010800001000050200316034200370080000102004120041200412004120041
80024200401500412580010108000010800005064000012002120040200409996031002080010208000020160000200402004011800211091010800001000050200416044200370080000102004120041200412004120041
8002420040150242522580010108000010800005064000012002120040200409996031004680010208000020160000200402004011800211091010800001000050200416044200370080000102004120041200412004120041
80024200401500412580010108000010800005064000012002120040200409996031002080010208000020160000200402004011800211091010800001000050200416043200370080000102004120041200412004120041
80024200401500412580010108000010800005064000012002120040200409996031002080010208000020160000200402004011800211091010800001000150200316044200370080000102004120041200412004120041
80024200401500412580010108000010800005064000012002120040200409996031002080010208000020160000200402004011800211091010800001000050200316044200370080000102004120041200412004120041
80024200401500412580010108000010800005064000012002120040200409996031002080010208000020160000200402004011800211091010800001000050200416043200370080000102004120041200412004120041
80024200401500412580010108000010800005064000012002120040200409996031002080010208000020160000200402004011800211091010800001000050200416034200370080000102004120041200412004120041