Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRSQRTS (vector, 8H)

Test 1: uops

Code:

  frsqrts v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100440373100061340725100010001000531908040184037403732583389510001000200040374037111001100000073116113473100040384038403840384038
100440373000061340725100010001000531908040184037403732583389510001000200040374037111001100000073116113473100040384038403840384038
100440373000061340725100010001000531908040184037403732583389510001000200040374037111001100000073116113473100040384038408640384038
100440373000061340725100010001000531908040184037403732583389510001160200040374037111001100004073116113473100040384038403840384038
100440373100061340725100010001000531908040184037403732583389510001000200040374037111001100000073116113473100040384038403840384038
100440373100961340725100010001000531908140184037403732583389510001000200040374037111001100000073116113473100040384038403840384038
100440373000061340725100010001000531908040184037403732583389510001000200040374037111001100000073116113473100040384038403840384038
100440373000061340725100010001000531908040184037403732583389510001000200040374037111001100000073116113473100040384038403840384038
100440373000061340725100010001000531908040184037403732583389510001000200040374037111001100000073116113473100040384038403840384038
100440373010061340725100010001000531908040184037403732583389510001000200040374037111001100000073116113473100040384038403840384038

Test 2: Latency 1->2

Code:

  frsqrts v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020440037299000000061394072510100100100001001000050057069081400184003740037381083387451010020010000200200004003740037111020110099100100100001000000000071021652394790100001004003840038400384003840038
1020440037300000000082394072510100100100001001000050057069081400184003740037381083387451010020010000200200004003740037111020110099100100100001000000000071021643395510100001004003840038400384003840038
10204404183031099106552816598393892061020214410054144105927785719434040298404184046938139463890811476224114922302264040467404561011020110099100100100001002251203153809172105343978429100001004046740469404654047140374
102044051830301891197792070893932620310199150100601491133275857208680402984050240420381444838929114792141148723422984404614046710110201100991001001000010024200035953271021622394790100001004003840038400384003840038
1020440037300000000061394072510100100100001001000050057069080400184003740037381083387451010020010000200200004003740037111020110099100100100001000000000071021622394790100001004003840038400384003840038
1020440037300000000061394072510100100100001001000050057069080400184003740037381083387451010020010000200200004003740037111020110099100100100001000000000071021622394790100001004003840038400384003840038
1020440037300000000082394072510100100100001001000050057069080400184003740037381083387451010020010000200200004003740037111020110099100100100001000000000071021622394790100001004003840038400384003840038
1020440037300000000061394072510100100100001001000050057069080400184003740037381083387451010020010000200200004003740037111020110099100100100001000000000071021622394790100001004003840038400384003840038
1020440037300000000061394072510100100100001001000050057069080400184003740037381083387451010020010000200200004003740037111020110099100100100001000000000071021622394790100001004003840038400384003840038
1020440037300000000061394072510100100100001001000050057069081400184003740037381083387451010020010000200200004003740037111020110099100100100001000000000071021622394790100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100244003729900061394072510010101000010100005057069080400180400374003738130338767100102010000202000040037400371110021109101010000100000640216223947310000104003840038400384003840038
100244003730000061394072510010101000010100005057069080400180400374003738130338767100102010000202000040037402241110021109101010000100000640216223947310000104003840038400384003840038
1002440037299000726394072510010101000010100005057069080400180400374003738130338767100102010000202000040037400371110021109101010000100000640216223947310000104003840038400384003840038
100244003730000061394072510010101000010100005057069080400183400374003738130338767100102010000202000040037400371110021109101010000100000640216223947310000104003840038400384003840038
100244003729900061394072510010101000010100005057069080400180400374003738130338767100102010000202000040037400371110021109101010000100000640216223947310000104003840038400384003840038
100244003730000061394072510010101000010100005057069080400180400374003738130338767100102010000202000040037400371110021109101010000100000640216223947310000104003840038400384003840038
100244003729900061394072510010101000010100005057069080400180400374003738130338767100102010000202000040037401791110021109101010000100000661216223947310000104003840038400384003840038
100244003729900061394072510010101000610100005057069080400180400374003738130338767100102010000202000040037400371110021109101010000100001640216223947310000104003840038400384003840038
100244003730000061394072510010101000010100005057069080400180400374003738130338767100102010000202000040037400371110021109101010000100060640216223947310000104003840038400384003840038
100244003730000061394072510010101000010100005057069080400180400374003738130338767100102010000202000040037400371110021109101010000100000640216223947310000104003840078400384003840038

Test 3: Latency 1->3

Code:

  frsqrts v0.8h, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020440037300006139407251010010010000100100005005706908400184003740037381083387451010020010000200200004003740037111020110099100100100001000000071021611394790100001004003840038400384003840038
1020440037300006139407251010010010000100100005005706908400184003740037381083387451010020010000200200004003740037111020110099100100100001000000071011611394790100001004003840038400384003840038
10204400373000047839407251010010010000100100005005706908400184003740037381083387451010020010000200200004003740037511020110099100100100001000000071032511394790100001004003840038400384003840038
1020440037300006139407251010010010000100100005005706908400184003740037381083387451010020010000200200004003740037111020110099100100100001000000071011611394790100001004003840038400384003840038
1020440037300006139407251010010010000100100005005706908400184003740037381083387451010020010000200200004003740037111020110099100100100001000000071011611394790100001004003840038400384003840038
1020440037300008239407251010010010000100100005005706908400184003740037381083387451010020010000200200004003740037111020110099100100100001000000071011611394790100001004003840038400384003840038
1020440037299006139407251010010010000100100005005706908400184003740037381083387451010020010000200200004003740037111020110099100100100001000000071011611394790100001004003840038400384003840038
10204400373000015639407251010010010000100100005005706908400184003740037381083387451010020010000200200004003740180111020110099100100100001000000073411611394790100001004003840038400384003840038
1020440037300006139407251010010010000100100005005706908400184003740037381083387451010020010000200200004003740037111020110099100100100001000000071011611394790100001004003840038400384003840038
1020440037300006139407251010010010000100100005005706908400184003740037381083387451010020010000200200004003740037111020110099100100100001000000071011611394790100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fbranch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024400373000613940725100101010000101000050570690804001840037400373813003387671001020100002020000400374003711100211091010100001000640316223947310000104003840038400384003840038
10024400373000613940725100101010000101000050570690814001840037400373813003387671001020100002020000400374003711100211091010100001000640216223947310000104003840038400384003840038
10024400373000613940725100101010000101000050570690814001840037400373813003387671001020100002020000400374003711100211091010100001000640216223947310000104003840038400384003840038
10024400373000613940725100101010000101000050570690804001840037400373813003387671001020100002020000400374003711100211091010100001000640224223947310000104003840038400384003840083
10024400373003613940725100101010000101000050570690804001840037400373813003387671001020100002020000400374003711100211091010100001000640216223947310000104003840038400384003840038
10024400373000613940725100101010000101000050570690804001840037400373813003387671001020100002020000400374003711100211091010100001000640216223947310000104003840038400384003840038
100244003730007263940725100101010000101000050570690804001840037400373813003387671001020100002020000400374003711100211091010100001000640316223947310000104003840038400384003840038
10024400373000613940725100101010000101000050570690804001840037400373813003387671001020100002020000400374003711100211091010100001000640216223947310000104003840038400384003840038
10024400373000613940725100101010000101000050570690804001840037400373813003387671001020100002020000400374017911100211091010100001000640216223947310000104003840038400384003840038
10024400373000613940725100101010000101000050570690804001840037400373813003387671001020100002020000400374003711100211091010100001000640216223947310000104003840038400384003840038

Test 4: throughput

Count: 8

Code:

  frsqrts v0.8h, v8.8h, v9.8h
  frsqrts v1.8h, v8.8h, v9.8h
  frsqrts v2.8h, v8.8h, v9.8h
  frsqrts v3.8h, v8.8h, v9.8h
  frsqrts v4.8h, v8.8h, v9.8h
  frsqrts v5.8h, v8.8h, v9.8h
  frsqrts v6.8h, v8.8h, v9.8h
  frsqrts v7.8h, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9d9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042004915000000001092580100100800001008000050064000000200212004020040997339998801002008000020016000020040200401180201100991001008000001000000000005110021611200370800001002004120041200412004120041
80204200401500000000422580100100800001008000050064000000200212004020040997339998801002008000020016000020040200401180201100991001008000001000000000005110011611200890800001002004120041200412004120041
80204200401500000000422580100100800001008000050064000000200212004020040997339998801002008000020016000020040200401180201100991001008000001000000000005110011611200370800001002004120041200412004120041
802042004015000000004492580100100800001008000050064000000200212004020040997339998801002008000020016000020040200401180201100991001008000001000000000005110021611200370800001002004120041200412004120041
80204200401500000000422580100100800001008000050064000010200212004020040997339998801002008000020016000020040200401180201100991001008000001000000000005110011611200370800001002004120041200412004120041
80204200401500000213002322580100100800001008000050064000010200212004020040997339998801002008000020016000020040200401180201100991001008000001000000000005110011611200370800001002004120041200412004120041
80204200401500000000422580100100800001008000050064000010200212004020040997339998801002008000020016000020040200401180201100991001008000001000000000005110011611200370800001002004120041200412004120041
802042004015000001200422580100100800001008000050064000010200212004020040997339998801002008000020016000020040200401180201100991001008000001000000020005110021611200370800001002004120041200412004120041
802042004015000000004272580100100800001008000050064000000200212004020040997339998801002008000020016000020040200401180201100991001008000001000000000005110011611200370800001002004120041200412004120041
80204200401500000000422580100100800001008000050064000000200212004020040997339998801002008000020016085020040200401180201100991001008000001000000000005110011611200370800001002004120041200412004120041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004015000412580010108000010800005064000012002120040200409996310020800102080000201600002004020040118002110910108000010502018316442003780000102004120041200412004120041
800242004015000852580010108000010800005064000012002120040200409996310020800102080000201600002004020040118002110910108000010502024316422003780000102004120041200412004120041
800242004015000412580010108000010800005064000002002120040200409996310020800102080000201600002004020040118002110910108000010502018416442003780000102004120041200412004120041
800242004015000412580010108000010800005064000002007220040200409996310020800102080000201600002004020040118002110910108000010502021416432003780000102004120041200412004120041
800242004015000412580010108000010800005064000002002120040200409996310020800102080000201600002004020040118002110910108000010502018316552003780000102004120041200412004120041
80024200401500018882580010108000010800005064000002002120040200409996310020800102080000201600002024920040118002110910108000010502018516442003780000102004120041200412004120041
800242004015000412580010108000010800005064000002002120040200409996310020800102080000201600002004020040118002110910108000010502021316322003780000102004120041200412004120041
800242004015000622580010108000010800005064000012002120040200409996310020800102080000201600002004020040118002110910108000010502018316352003780000102004120041200412004120041
800242004015000412580010108000010800005064000012002120040200409996310020800102080000201600002004020040118002110910108000010502018416442003780000102004120041200412004120041
800242004015000412580010108000010800005064000012002120040200409996310020800102080000201600002004020040118002110910108000010502018416432003780000102004120041200412004120041