Firestorm: FSQRT (scalar, D) measurements

Code:

  fsqrt d0, d0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	13037	97	132	0	61	11540	25	1000	1000	1000	457953	1	13018	13037	13037	12248	3	12895	1000	1000	1000	13037	13037	1	1	1001	1000	0	73	1	16	1	1	12431	1000	13038	13038	13038	13038	13038
1004	13037	98	12	264	71	11540	25	1000	1000	1000	457953	1	13018	13037	13037	12248	3	12895	1000	1000	1000	13037	13037	1	1	1001	1000	0	73	1	16	1	1	12431	1000	13038	13038	13038	13038	13038
1004	13037	98	9	0	61	11540	25	1000	1000	1000	457953	1	13018	13037	13037	12248	3	12895	1000	1000	1000	13037	13037	1	1	1001	1000	0	73	1	16	1	1	12431	1000	13038	13038	13038	13038	13038
1004	13037	97	6	0	61	11540	25	1000	1000	1000	457953	1	13018	13037	13037	12248	3	12895	1000	1000	1000	13037	13037	1	1	1002	1000	0	73	1	16	1	1	12431	1000	13038	13038	13038	13038	13038
1004	13037	97	24	0	61	11540	25	1000	1000	1000	457953	1	13018	13037	13037	12248	3	12895	1000	1000	1000	13037	13037	1	1	1001	1000	0	73	1	16	1	1	12431	1000	13038	13038	13038	13038	13038
1004	13037	98	0	0	61	11540	25	1000	1000	1000	457953	1	13018	13037	13037	12248	3	12895	1000	1000	1000	13037	13037	1	1	1001	1000	0	73	1	16	1	1	12431	1000	13038	13038	13038	13038	13038
1004	13037	97	0	0	149	11540	25	1000	1000	1000	457953	1	13018	13037	13037	12248	3	12895	1000	1000	1000	13037	13037	1	1	1001	1000	0	73	1	16	1	1	12431	1000	13038	13038	13038	13038	13038
1004	13037	98	0	0	61	11540	25	1000	1000	1000	457953	1	13018	13037	13037	12248	3	12895	1000	1000	1000	13037	13037	1	1	1001	1000	0	73	1	16	1	1	12431	1000	13038	13038	13038	13038	13038
1004	13037	97	0	0	61	11540	25	1000	1000	1000	457953	1	13018	13037	13037	12248	3	12895	1000	1000	1000	13037	13037	1	1	1001	1000	0	73	1	16	1	1	12431	1000	13038	13038	13038	13038	13038
1004	13037	98	0	0	61	11540	25	1000	1000	1000	457953	1	13018	13037	13037	12248	3	12895	1000	1000	1000	13037	13037	1	1	1001	1000	0	73	1	16	1	1	12431	1000	13038	13038	13038	13038	13038

Test 2: Latency 1->2

Code:

  fsqrt d0, d0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	130037	974	0	0	0	0	0	0	251	119540	25	10100	100	10000	100	10000	500	4660953	1	130018	130037	130037	128105	7	128740	10100	200	10008	200	10008	130037	130037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	718	0	17	0	0	129444	0	10000	100	130038	130038	130038	130038	130038
10204	130037	974	0	0	0	0	174	0	726	119540	25	10100	100	10000	100	10000	500	4660953	0	130018	130037	130037	128105	7	128740	10100	200	10008	200	10008	130037	130037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	717	0	16	0	0	129444	0	10000	100	130038	130038	130038	130038	130038
10204	130037	974	0	0	0	0	0	0	1684	119540	25	10100	100	10000	100	10000	500	4660953	1	130018	130037	130037	128105	6	128741	10100	200	10008	200	10008	130037	130037	2	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	718	0	16	0	0	129443	0	10000	100	130038	130038	130038	130038	130038
10204	130037	974	0	0	0	0	0	0	61	119540	25	10100	100	10000	100	10000	598	4660953	1	130018	130037	130037	128105	14	128740	10100	200	10008	200	10008	130037	130037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	717	0	16	0	0	129443	0	10000	100	130038	130038	130038	130038	130038
10204	130037	974	0	0	0	0	0	0	61	119540	25	10100	100	10000	100	10000	500	4660953	0	130018	130037	130037	128105	6	128740	10100	200	10008	200	10008	130037	130037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	718	0	16	0	0	129444	0	10000	100	130038	130038	130038	130038	130038
10204	130037	974	0	0	0	0	0	0	61	119540	25	10100	100	10000	100	10000	500	4660953	0	130018	130037	130037	128105	6	128740	10100	200	10008	200	10008	130037	130037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	717	0	16	0	0	129444	0	10000	100	130038	130038	130038	130038	130038
10204	130037	974	0	0	0	0	0	0	61	119532	25	10100	100	10000	100	10000	500	4660953	1	130018	130037	130037	128105	7	128741	10100	200	10008	200	10008	130037	130037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	267	1	1	1	718	0	16	0	0	129444	0	10000	100	130038	130038	130038	130038	130038
10204	130037	974	0	0	0	0	0	0	61	119540	25	10100	100	10000	100	10000	500	4660953	1	130018	130037	130037	128105	7	128741	10100	200	10008	200	10008	130037	130037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	300	1	1	1	718	0	16	0	0	129444	0	10000	100	130038	130038	130038	130038	130038
10204	130037	974	0	0	0	0	63	0	61	119540	25	10100	100	10000	100	10152	500	4660953	1	130018	130037	130037	128105	6	128741	10100	200	10008	200	10008	130037	130037	1	1	10201	100	99	100	100	10000	100	0	0	78	0	3	1	1	1	717	0	16	0	0	129444	0	10000	100	130038	130038	130038	130038	130038
10204	130037	974	0	0	0	0	0	0	61	119540	25	10100	100	10000	100	10000	500	4660953	1	130018	130037	130037	128105	7	128741	10100	200	10008	200	10008	130037	130037	1	1	10201	100	99	100	100	10000	100	0	0	82	0	0	1	1	1	718	0	16	0	0	129443	0	10000	100	130179	130085	130038	130038	130038

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	130037	974	0	0	0	0	61	119540	25	10010	10	10000	10	10000	50	4660953	1	130018	130037	130037	128120	0	3	128767	10010	20	10000	20	10000	130037	130037	1	1	10021	10	9	10	10	10000	10	0	9	0	0	640	2	16	2	2	129431	10000	10	130038	130038	130038	130038	130038
10024	130037	974	0	57	0	0	96	119540	25	10010	10	10000	10	10000	50	4660953	1	130018	130037	130037	128120	0	3	128767	10010	20	10000	20	10000	130037	130037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	129431	10000	10	130038	130038	130038	130038	130038
10024	130037	974	0	0	0	0	61	119540	25	10010	10	10000	10	10000	50	4660953	1	130018	130037	130037	128120	0	3	128767	10010	20	10000	20	10000	130037	130037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	129431	10000	10	130038	130038	130038	130038	130038
10024	130037	974	0	0	0	0	61	119540	25	10010	10	10000	10	10000	50	4660953	1	130018	130037	130037	128120	0	3	128767	10010	20	10000	20	10000	130037	130037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	129431	10000	10	130038	130038	130038	130038	130038
10024	130037	974	0	0	0	0	61	119540	25	10010	10	10008	10	10000	50	4660953	1	130018	130037	130037	128120	0	3	128767	10010	20	10000	20	10000	130037	130037	1	1	10021	10	9	10	10	10000	10	85	3	0	0	640	2	16	2	2	129431	10000	10	130038	130038	130038	130038	130038
10024	130037	974	0	0	0	0	61	119540	25	10010	10	10000	10	10000	50	4660953	1	130018	130037	130037	128184	0	3	128767	10010	20	10000	20	10000	130037	130037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	129431	10000	10	130038	130038	130038	130038	130038
10024	130037	974	0	0	0	0	916	119540	25	10010	10	10000	10	10000	50	4660953	1	130018	130037	130037	128120	0	3	128767	10010	20	10000	20	10000	130037	130037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	129431	10000	10	130038	130038	130038	130038	130038
10024	130037	974	0	0	0	0	61	119540	25	10010	10	10000	10	10000	50	4660953	1	130018	130037	130037	128120	0	3	128767	10010	20	10000	20	10000	130037	130037	1	1	10021	10	9	10	10	10000	10	88	0	0	0	640	2	16	2	2	129431	10000	10	130038	130038	130038	130038	130038
10024	130037	974	0	0	0	0	61	119540	25	10010	10	10000	10	10000	50	4660953	1	130018	130037	130037	128120	0	3	128767	10010	20	10000	20	10000	130037	130037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	129431	10000	10	130038	130038	130038	130038	130038
10024	130037	974	0	0	0	0	61	119540	25	10010	10	10000	10	10000	50	4660953	1	130018	130037	130037	128139	0	3	128767	10010	20	10000	20	10000	130037	130037	1	1	10021	10	9	10	10	10000	10	93	0	0	0	640	2	16	2	2	129431	10000	10	130038	130038	130038	130038	130038

Test 3: throughput

Count: 8

Code:

  fsqrt d0, d8
  fsqrt d1, d8
  fsqrt d2, d8
  fsqrt d3, d8
  fsqrt d4, d8
  fsqrt d5, d8
  fsqrt d6, d8
  fsqrt d7, d8

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	160048	1198	0	0	1275	79937	25	80100	100	80034	100	80000	500	5677984	1	0	160029	160048	160048	149895	6	150002	80100	200	80008	200	80008	160048	160048	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5117	0	0	1	16	0	0	159981	80000	100	160049	160049	160049	160049	160049
80204	160048	1199	0	0	61	79937	25	80100	100	80000	100	80000	500	5677984	0	0	160029	160048	160048	149895	6	150002	80100	200	80008	200	80008	160048	160048	1	1	80201	100	99	100	100	80000	100	1	3	1	1	1	5117	0	0	0	16	0	0	159981	80000	100	160049	160049	160049	160049	160049
80204	160048	1198	0	0	726	79937	25	80100	100	80000	100	80000	500	5677984	0	0	160029	160048	160048	149895	6	150002	80100	200	80008	200	80008	160048	160048	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5117	0	0	0	16	0	0	159981	80000	100	160049	160049	160049	160049	160049
80204	160048	1199	0	0	61	79937	25	80100	100	80000	100	80000	500	5677984	0	0	160029	160048	160048	149895	6	150002	80100	200	80008	200	80008	160048	160048	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5117	0	0	0	16	0	0	160051	80000	100	160049	160049	160049	160049	160049
80204	160048	1199	0	0	2780	79937	25	80100	100	80000	100	80000	500	5677984	0	0	160029	160048	160048	149895	6	150002	80100	200	80008	200	80008	160048	160048	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5117	0	0	0	16	0	0	159981	80000	100	160049	160049	160049	160049	160049
80204	160048	1199	0	0	298	79937	25	80117	100	80000	100	80000	500	5677984	1	0	160029	160048	160048	149895	6	150002	80100	200	80008	200	80008	160048	160048	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5117	0	0	0	16	0	0	159981	80000	100	160049	160049	160049	160049	160049
80204	160048	1199	0	0	61	79937	25	80100	100	80000	100	80000	555	5677984	1	0	160029	160048	160048	149895	6	150002	80100	200	80008	200	80008	160048	160048	1	1	80201	100	99	100	100	80000	100	1	3	1	1	1	5117	0	0	0	16	0	0	159981	80000	100	160049	160049	160049	160049	160049
80204	160106	1198	0	0	61	79937	25	80100	100	80000	100	80000	500	5677984	0	0	160029	160048	160048	149895	6	150002	80100	200	80008	200	80008	160048	160048	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5117	0	0	0	16	0	0	159981	80000	100	160049	160049	160049	160049	160049
80204	160048	1198	0	0	631	79937	25	80100	100	80000	100	80000	500	5677984	0	0	160029	160048	160048	149895	6	150002	80100	200	80008	200	80008	160048	160048	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5117	0	0	0	16	0	0	159981	80000	100	160049	160049	160049	160049	160049
80204	160048	1199	654	0	2170	79937	25	80100	100	80000	100	80049	500	5677984	0	0	160029	160048	160048	149895	6	150002	80100	200	80008	200	80008	160048	160048	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5117	0	0	0	16	0	0	159981	80000	100	160049	160049	160049	160049	160049

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	160048	1199	42	0	61	79937	25	80010	10	80000	10	80000	50	5677984	0	1	160029	160048	160048	149910	0	3	150028	80010	20	80000	20	80000	160048	160048	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	1	16	0	1	1	159971	0	0	80000	10	160049	160049	160049	160049	160049
80024	160048	1198	0	0	61	79937	25	80010	10	80000	10	80051	50	5677984	0	1	160029	160048	160048	149910	0	3	150028	80010	20	80000	20	80000	160048	160048	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	1	16	0	1	1	159971	0	0	80000	10	160049	160049	160049	160049	160049
80024	160048	1198	0	0	61	79937	25	80010	10	80000	10	80000	50	5677984	0	1	160029	160048	160048	149910	0	3	150028	80010	20	80000	20	80000	160048	160048	1	1	80021	10	9	10	10	80000	10	0	2	3	0	0	5035	0	1	17	0	1	1	159971	0	0	80000	10	160049	160049	160049	160049	160049
80024	160048	1199	0	0	61	79937	25	80010	10	80000	10	80000	50	5677984	0	1	160029	160048	160048	149910	0	3	150028	80010	20	80000	20	80000	160048	160048	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	1	16	0	1	1	159971	0	0	80000	10	160049	160049	160049	160049	160049
80024	160048	1199	0	0	61	79937	25	80010	10	80000	10	80000	50	5677984	0	1	160029	160048	160048	149910	0	3	150028	80010	20	80000	20	80000	160048	160048	1	1	80021	10	9	10	10	80000	10	0	0	0	0	1	5020	0	1	16	0	1	1	159971	0	0	80000	10	160049	160049	160049	160049	160049
80024	160048	1199	0	0	61	79937	25	80010	10	80000	10	80000	50	5677984	0	1	160029	160048	160048	149910	0	3	150028	80010	20	80000	20	80000	160048	160048	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	2	16	0	1	1	159971	0	0	80000	10	160049	160049	160049	160049	160049
80024	160048	1199	0	0	61	79937	25	80010	10	80000	10	80000	50	5677984	0	1	160029	160048	160048	149910	0	3	150028	80010	20	80000	20	80000	160048	160048	1	1	80021	10	9	10	10	80000	10	5	0	0	0	0	5020	0	1	16	0	1	1	159971	0	0	80000	10	160049	160049	160049	160049	160049
80024	160048	1199	0	0	434	79937	25	80027	10	80017	10	80051	50	5677984	0	1	160029	160048	160048	149910	0	3	150028	80010	20	80000	20	80000	160048	160048	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	1	16	0	1	1	159971	0	0	80000	10	160049	160049	160049	160049	160049
80024	160048	1199	0	0	726	79937	25	80010	10	80000	10	80000	50	5677984	0	1	160029	160048	160048	149910	0	3	150028	80010	20	80000	20	80000	160048	160048	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	1	16	0	1	1	159971	0	0	80000	10	160049	160049	160049	160049	160049
80024	160048	1199	0	0	66	79937	25	80010	10	80000	10	80000	50	5677984	0	1	160029	160048	160048	149910	0	3	150028	80010	20	80000	20	80000	160048	160048	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	1	16	0	1	1	159971	0	0	80000	10	160049	160049	160049	160049	160049

FSQRT (scalar, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations