Firestorm: FSQRT (scalar, H) measurements

Code:

  fsqrt h0, h0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	8132	61	0	0	48	0	61	6720	25	1000	1000	1000	281563	8018	8037	8037	7493	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	0	0	3	0	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038
1004	8037	60	0	0	0	0	103	6720	25	1000	1000	1000	281261	8018	8037	8037	7493	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	7676	1000	8038	8038	8133	8038	8038
1004	8037	60	0	0	0	0	346	6720	49	1003	1000	1000	281261	8018	8037	8037	7493	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038
1004	8037	60	0	0	0	0	61	6720	25	1000	1000	1000	281261	8018	8037	8037	7493	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	7726	1000	8038	8038	8038	8038	8038
1004	8037	60	0	0	0	0	61	6720	25	1000	1000	1000	281261	8018	8037	8037	7493	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038
1004	8037	60	0	0	0	0	61	6720	25	1000	1000	1000	281261	8018	8037	8037	7493	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038
1004	8037	60	0	0	0	0	61	6720	25	1000	1000	1000	281261	8018	8037	8037	7493	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	0	2	0	0	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038
1004	8037	60	0	0	0	0	61	6720	25	1000	1000	1000	281261	8018	8037	8037	7493	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038
1004	8037	60	0	0	0	0	61	6720	25	1003	1000	1000	281261	8018	8037	8037	7493	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038
1004	8037	60	0	0	0	88	61	6720	25	1000	1000	1000	281261	8018	8037	8037	7493	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	2	3	0	0	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038

Test 2: Latency 1->2

Code:

  fsqrt h0, h0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 8.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	80037	600	0	0	0	0	42	0	1345	69720	25	10123	100	10000	100	10000	500	2864261	1	80158	80037	80037	78343	3	78745	10100	200	10000	200	10056	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	79676	0	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	0	30	0	61	69720	25	10100	100	10000	100	10000	500	2864261	1	80018	80037	80037	78343	3	78745	10100	200	10224	200	10000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	79676	0	10000	100	80038	80224	80038	80038	80038
10204	80037	599	0	0	0	0	543	0	726	69720	25	10100	100	10000	100	10152	500	2864261	1	80018	80037	80037	78343	3	78745	10100	200	10000	200	10000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	79676	0	10000	100	80038	80038	80038	80038	80038
10204	80037	600	0	0	0	0	0	0	61	69720	25	10100	100	10000	100	10000	500	2864261	1	80018	80037	80037	78343	3	78745	10100	200	10000	200	10000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	79704	0	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	0	21	0	61	69720	25	10100	124	10000	100	10000	500	2864261	1	80018	80037	80037	78343	3	78745	10100	200	10218	200	10000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	79821	0	10000	100	80038	80038	80038	80180	80038
10204	80037	599	0	0	0	4	60	0	61	69720	25	10100	100	10000	100	10000	500	2864261	1	80018	80037	80037	78343	3	78745	10100	200	10000	200	10000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	4	2	0	0	0	710	1	16	1	1	79676	0	10000	100	80038	80038	80038	80038	80038
10204	80037	600	0	0	0	0	51	0	6778	69720	25	10100	100	10000	100	10000	500	2864261	1	80018	80037	80037	78343	3	78745	10100	200	10000	200	10000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	79676	14	10000	100	80038	80038	80038	80038	80038
10204	80037	600	0	0	0	0	537	0	61	69720	25	10100	100	10000	100	10000	500	2864261	1	80018	80037	80037	78343	3	78745	10100	200	10000	200	10000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	6	0	0	0	0	710	1	16	1	1	79676	0	10000	100	80038	80038	80038	80038	80038
10204	80037	600	0	0	0	0	93	0	103	69720	25	10135	100	10000	100	10000	500	2864261	1	80018	80037	80037	78343	3	78745	10100	200	10000	200	10000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	2	79676	0	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	0	36	0	61	69720	25	10100	100	10000	100	10000	500	2864261	1	80018	80132	80037	78343	3	78745	10138	200	10000	200	10227	80037	80037	1	1	10201	100	99	100	100	10000	100	0	1	0	0	0	0	0	0	0	710	1	16	1	1	79676	23	10000	100	80038	80038	80038	80038	80038

1000 unrolls and 10 iterations

Result (median cycles for code): 8.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	80037	600	0	0	0	0	42	0	0	61	69720	25	10010	10	10000	10	10000	50	2864261	0	80018	80037	80037	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	79676	0	10000	10	80038	80038	80038	80038	80038
10024	80037	600	0	0	0	0	270	0	0	61	69720	25	10010	10	10000	10	10000	50	2864261	1	80018	80037	80037	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	79676	0	10000	10	80038	80038	80038	80038	80038
10024	80037	599	0	0	0	0	15	0	0	61	69720	25	10010	10	10000	10	10000	50	2864261	0	80018	80037	80037	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	2	0	910	5	160	3	4	80362	1	10000	10	80922	81224	80926	80943	80925
10024	80935	606	0	0	19	19	2802	1760	0	11558	69454	373	10067	16	10054	11	10722	65	2869999	0	80648	80180	80886	78705	88	79379	10737	24	11083	24	11018	80940	80981	20	1	10021	10	9	10	10	10000	10	2	0	1	2	58930	0	0	640	2	16	5	4	80252	6	10000	10	81033	80981	80983	81027	80936
10024	81014	610	1	1	27	24	2904	2024	1	15063	69720	258	10066	13	10000	10	10228	50	2864261	0	80018	80037	80037	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	3	2	79676	1	10000	10	80038	80038	80038	80038	80038
10024	80037	648	0	0	0	0	48	0	0	1219	69720	25	10010	10	10000	10	10000	50	2864261	0	80053	80084	80037	78383	6	78767	10088	20	10000	20	10051	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	79676	0	10000	10	80038	80038	80038	80038	80038
10024	80277	601	1	1	0	0	30	0	0	3604	69720	25	10010	10	10003	10	10000	50	2864261	0	80018	80037	80037	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	79676	0	10000	10	80038	80038	80038	80038	80038
10024	80037	599	0	0	0	0	12	0	0	61	69720	25	10010	10	10000	10	10000	50	2864261	1	80018	80037	80037	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	79676	0	10000	10	80038	80038	80038	80038	80038
10024	80037	600	0	0	0	4	27	0	0	61	69720	25	10010	10	10000	10	10000	50	2864261	0	80018	80037	80037	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	79676	0	10000	10	80038	80038	80038	80038	80038
10024	80037	599	0	0	0	0	0	0	0	61	69720	25	10010	10	10003	10	10000	50	2864261	0	80018	80037	80037	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	79676	0	10000	10	80038	80038	80038	80038	80038

Test 3: throughput

Count: 8

Code:

  fsqrt h0, h8
  fsqrt h1, h8
  fsqrt h2, h8
  fsqrt h3, h8
  fsqrt h4, h8
  fsqrt h5, h8
  fsqrt h6, h8
  fsqrt h7, h8

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	160043	1198	0	0	0	61	79937	25	80100	100	80000	100	80000	500	5677984	160024	0	160043	160043	149895	0	6	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	1	1	1	5117	1	16	0	0	159981	80000	100	160044	160044	160044	160044	160044
80204	160043	1198	0	0	684	61	79937	25	80100	100	80000	100	80000	500	5677984	160024	0	160043	160043	149895	0	6	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	1	1	1	5117	0	16	0	0	159981	80000	100	160044	160044	160044	160044	160044
80204	160043	1199	0	0	0	61	79937	25	80100	100	80000	100	80000	500	5677984	160024	0	160043	160043	149895	0	6	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	1	1	1	5117	0	16	0	0	159981	80000	100	160044	160044	160044	160044	160044
80204	160043	1199	0	0	0	61	79937	25	80100	100	80000	100	80000	500	5677984	160024	0	160043	160043	149895	0	6	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	1	0	3	1	1	1	5117	0	16	0	0	159981	80000	100	160044	160044	160044	160044	160044
80204	160043	1199	5	0	0	726	79937	25	80100	100	80000	100	80000	500	5677984	160024	0	160043	160043	149895	0	6	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	3	1	1	1	5117	0	17	0	0	159981	80000	100	160044	160044	160044	160044	160044
80204	160043	1198	0	0	24	61	79937	25	80100	100	80000	100	80000	500	5677984	160024	0	160043	160043	149895	0	6	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	1	1	1	5117	0	16	0	0	159981	80000	100	160044	160044	160044	160044	160044
80204	160043	1198	0	0	0	726	79937	25	80100	100	80000	100	80000	500	5677984	160024	0	160043	160043	149895	0	6	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	1	1	1	5117	0	16	0	0	159981	80000	100	160044	160044	160044	160044	160044
80204	160043	1199	0	0	0	61	79937	25	80100	100	80000	100	80000	500	5677984	160024	0	160043	160043	149895	0	6	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	1	1	1	5117	0	16	0	0	159981	80000	100	160044	160044	160044	160044	160044
80204	160043	1199	0	0	0	726	79937	25	80100	100	80000	100	80000	500	5677984	160024	0	160043	160043	149895	0	6	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	15	1	1	1	5117	0	16	0	0	159981	80000	100	160044	160044	160044	160044	160044
80204	160043	1199	3	0	0	61	79937	25	80100	100	80000	100	80000	500	5677984	160024	0	160043	160043	149895	0	6	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	1	1	1	5117	0	16	0	0	159981	80000	100	160044	160044	160044	160044	160044

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	160043	1199	0	0	0	61	79937	25	80010	10	80000	10	80000	50	5677984	0	160077	0	160043	160090	149910	0	3	150023	80010	20	80076	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	0	0	4	16	0	0	0	2	4	159969	0	80000	10	160044	160044	160044	160044	160044
80024	160043	1198	0	0	0	726	79937	25	80010	10	80000	10	80000	50	5677984	0	160024	0	160043	160043	149910	0	3	150023	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	122	0	0	0	5020	0	0	0	4	16	0	0	0	4	4	159969	0	80000	10	160044	160044	160044	160044	160044
80024	160043	1199	0	0	0	61	79937	25	80010	10	80000	10	80000	50	5677984	0	160024	0	160043	160043	149910	0	3	150023	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	152	0	0	0	5020	0	0	0	4	16	0	0	0	4	3	159969	0	80000	10	160044	160044	160044	160083	160044
80024	160043	1199	0	0	0	726	79937	25	80010	10	80000	10	80000	50	5677984	0	160024	3	160043	160043	149910	0	3	150023	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	0	0	4	16	0	0	0	4	2	159969	0	80000	10	160044	160044	160044	160044	160044
80024	160043	1199	0	0	0	61	79937	25	80010	10	80000	10	80000	50	5677984	0	160024	0	160043	160043	149910	0	3	150023	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	0	0	2	16	0	0	0	4	2	159969	0	80000	10	160044	160044	160044	160044	160044
80024	160043	1199	1	243	372	726	79937	25	80010	10	80000	10	80000	50	5677984	0	160024	0	160043	160043	149910	0	3	150046	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	0	0	2	16	1	0	0	4	3	159969	0	80000	10	160044	160044	160044	160044	160044
80024	160043	1199	0	0	0	61	79937	25	80010	10	80000	10	80000	50	5677984	0	160024	0	160043	160043	149910	0	3	150023	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	0	0	2	16	0	0	0	4	2	159969	0	80000	10	160044	160044	160044	160044	160044
80024	160043	1199	0	0	0	61	79937	25	80010	10	80011	10	80000	50	5677984	0	160024	0	160043	160043	149910	0	3	150023	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	0	0	4	16	0	0	0	4	3	159969	0	80000	10	160044	160097	160044	160044	160044
80024	160043	1199	0	0	0	61	79937	25	80010	10	80000	10	80000	50	5677984	0	160024	0	160043	160043	149910	0	3	150023	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	148	0	0	0	5020	0	0	0	4	16	0	0	0	2	4	159969	0	80000	10	160044	160044	160044	160044	160044
80024	160043	1199	0	0	0	61	79937	25	80010	10	80000	10	80000	50	5677984	0	160024	0	160043	160043	149910	0	3	150023	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	3	0	4	16	0	0	0	4	4	159969	0	80000	10	160044	160044	160044	160044	160044

FSQRT (scalar, H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations