Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
fsqrt v0.2d, v0.2d
movi v0.16b, 1 movi v1.16b, 2
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 0.000
Load/store unit issues: 0.000
SIMD/FP unit issues: 1.000
| retire uop (01) | cycle (02) | 03 | 1e | 3f | 4e | 51 | schedule uop (52) | schedule simd uop (54) | dispatch simd uop (57) | ldst uops in schedulers (5b) | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map simd uop (7e) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd alu (9a) | l1d cache writeback (a8) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? simd retires (ee) | f5 | f6 | f7 | f8 | fd |
| 1004 | 13037 | 98 | 0 | 61 | 11540 | 25 | 1000 | 1000 | 1000 | 457953 | 13018 | 13037 | 13037 | 12248 | 3 | 12895 | 1000 | 1000 | 1000 | 13037 | 13037 | 1 | 1 | 1001 | 1000 | 5 | 3 | 73 | 1 | 16 | 1 | 1 | 12431 | 1000 | 13038 | 13038 | 13038 | 13038 | 13038 |
| 1004 | 13037 | 98 | 0 | 61 | 11540 | 25 | 1000 | 1000 | 1000 | 457953 | 13018 | 13037 | 13037 | 12248 | 3 | 12895 | 1000 | 1000 | 1000 | 13037 | 13037 | 1 | 1 | 1001 | 1000 | 6 | 0 | 73 | 1 | 16 | 1 | 1 | 12431 | 1000 | 13038 | 13038 | 13038 | 13038 | 13038 |
| 1004 | 13037 | 98 | 0 | 61 | 11540 | 25 | 1000 | 1000 | 1000 | 457953 | 13018 | 13037 | 13037 | 12248 | 3 | 12895 | 1000 | 1000 | 1000 | 13037 | 13037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 1 | 16 | 2 | 1 | 12431 | 1000 | 13038 | 13038 | 13038 | 13038 | 13038 |
| 1004 | 13037 | 97 | 0 | 61 | 11540 | 25 | 1000 | 1000 | 1000 | 457953 | 13018 | 13037 | 13037 | 12248 | 3 | 12895 | 1000 | 1000 | 1000 | 13037 | 13071 | 1 | 1 | 1001 | 1000 | 0 | 48 | 73 | 1 | 16 | 1 | 1 | 12431 | 1000 | 13038 | 13038 | 13038 | 13038 | 13038 |
| 1004 | 13037 | 98 | 15 | 61 | 11540 | 25 | 1000 | 1000 | 1000 | 457953 | 13018 | 13037 | 13037 | 12248 | 3 | 12895 | 1000 | 1000 | 1000 | 13037 | 13037 | 1 | 1 | 1001 | 1000 | 0 | 42 | 73 | 1 | 16 | 1 | 1 | 12431 | 1000 | 13038 | 13038 | 13038 | 13038 | 13038 |
| 1004 | 13037 | 97 | 0 | 61 | 11540 | 25 | 1000 | 1000 | 1000 | 457953 | 13018 | 13037 | 13037 | 12248 | 3 | 12895 | 1000 | 1000 | 1000 | 13037 | 13037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 12431 | 1000 | 13038 | 13038 | 13038 | 13038 | 13038 |
| 1004 | 13037 | 98 | 0 | 61 | 11540 | 25 | 1000 | 1000 | 1000 | 457953 | 13018 | 13037 | 13037 | 12248 | 3 | 12895 | 1000 | 1000 | 1000 | 13037 | 13037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 12431 | 1000 | 13038 | 13038 | 13038 | 13038 | 13038 |
| 1004 | 13037 | 97 | 0 | 61 | 11540 | 25 | 1000 | 1000 | 1000 | 457953 | 13018 | 13037 | 13037 | 12248 | 3 | 12895 | 1000 | 1000 | 1000 | 13037 | 13037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 12431 | 1000 | 13038 | 13038 | 13038 | 13038 | 13038 |
| 1004 | 13037 | 98 | 0 | 61 | 11540 | 25 | 1000 | 1000 | 1000 | 457953 | 13018 | 13037 | 13037 | 12248 | 3 | 12895 | 1000 | 1000 | 1000 | 13037 | 13037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 12431 | 1000 | 13038 | 13038 | 13038 | 13038 | 13038 |
| 1004 | 13037 | 97 | 9 | 61 | 11540 | 25 | 1000 | 1000 | 1000 | 457953 | 13018 | 13037 | 13037 | 12248 | 3 | 12895 | 1000 | 1000 | 1000 | 13037 | 13037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 12431 | 1000 | 13038 | 13038 | 13038 | 13038 | 13038 |
Code:
fsqrt v0.2d, v0.2d
movi v0.16b, 1 movi v1.16b, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 13.0037
| retire uop (01) | cycle (02) | 03 | 09 | l2 tlb miss data (0b) | 1e | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6b | 6d | 6e | map stall dispatch (70) | simd prf full (72) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | ld unit uop (a6) | l1d cache writeback (a8) | ac | branch cond mispred nonspec (c5) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ea | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10204 | 130037 | 974 | 0 | 0 | 0 | 701 | 119540 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4660953 | 0 | 130018 | 0 | 130037 | 130037 | 128098 | 0 | 3 | 128745 | 10100 | 200 | 10000 | 200 | 10000 | 130037 | 130037 | 2 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 2 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 129431 | 0 | 10000 | 100 | 130038 | 130038 | 130038 | 130038 | 130038 |
| 10204 | 130037 | 974 | 0 | 0 | 0 | 187 | 119540 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4660953 | 0 | 130018 | 0 | 130070 | 130037 | 128098 | 0 | 3 | 128745 | 10100 | 200 | 10000 | 200 | 10000 | 130037 | 130037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 129431 | 0 | 10000 | 100 | 130038 | 130038 | 130038 | 130038 | 130038 |
| 10204 | 130037 | 974 | 0 | 0 | 0 | 726 | 119540 | 25 | 10100 | 100 | 10000 | 100 | 10037 | 500 | 4660953 | 0 | 130018 | 0 | 130037 | 130037 | 128098 | 0 | 3 | 128745 | 10100 | 200 | 10000 | 200 | 10000 | 130037 | 130037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 3 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 129431 | 0 | 10000 | 100 | 130038 | 130038 | 130038 | 130038 | 130038 |
| 10204 | 130037 | 974 | 0 | 0 | 0 | 569 | 119540 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4660953 | 0 | 130018 | 0 | 130037 | 130037 | 128098 | 0 | 3 | 128745 | 10100 | 200 | 10000 | 200 | 10000 | 130037 | 130037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 129431 | 0 | 10000 | 100 | 130038 | 130038 | 130038 | 130038 | 130038 |
| 10204 | 130037 | 974 | 0 | 0 | 0 | 256 | 119540 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4660953 | 0 | 130018 | 0 | 130037 | 130037 | 128098 | 0 | 3 | 128745 | 10100 | 200 | 10000 | 200 | 10000 | 130037 | 130037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 129431 | 0 | 10000 | 100 | 130038 | 130038 | 130038 | 130038 | 130038 |
| 10204 | 130037 | 974 | 0 | 0 | 0 | 61 | 119540 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4660953 | 0 | 130018 | 0 | 130037 | 130037 | 128098 | 0 | 3 | 128745 | 10100 | 200 | 10000 | 200 | 10000 | 130037 | 130037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 129431 | 0 | 10000 | 100 | 130038 | 130038 | 130038 | 130038 | 130038 |
| 10204 | 130037 | 974 | 0 | 0 | 0 | 61 | 119540 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4660953 | 0 | 130018 | 0 | 130037 | 130037 | 128098 | 0 | 3 | 128745 | 10100 | 200 | 10000 | 200 | 10000 | 130037 | 130037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 129431 | 0 | 10000 | 100 | 130038 | 130038 | 130038 | 130038 | 130038 |
| 10204 | 130037 | 974 | 0 | 0 | 0 | 61 | 119540 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4660953 | 0 | 130018 | 0 | 130037 | 130037 | 128098 | 0 | 3 | 128745 | 10100 | 200 | 10000 | 200 | 10000 | 130037 | 130037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 1 | 710 | 1 | 16 | 1 | 1 | 129431 | 0 | 10000 | 100 | 130038 | 130038 | 130038 | 130038 | 130038 |
| 10204 | 130037 | 974 | 0 | 0 | 0 | 61 | 119540 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4660953 | 0 | 130018 | 0 | 130037 | 130037 | 128098 | 0 | 3 | 128745 | 10100 | 200 | 10000 | 200 | 10000 | 130037 | 130037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 3 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 129431 | 0 | 10000 | 100 | 130038 | 130038 | 130038 | 130038 | 130038 |
| 10204 | 130037 | 974 | 0 | 0 | 0 | 216 | 119540 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4660953 | 0 | 130018 | 0 | 130037 | 130037 | 128098 | 0 | 3 | 128745 | 10100 | 200 | 10000 | 200 | 10000 | 130037 | 130037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 129431 | 0 | 10000 | 100 | 130038 | 130038 | 130038 | 130038 | 130038 |
Result (median cycles for code): 13.0037
| retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 18 | 1e | 1f | 3a | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | ac | c2 | branch cond mispred nonspec (c5) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10024 | 130037 | 974 | 0 | 0 | 0 | 0 | 0 | 82 | 119540 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4660953 | 1 | 130018 | 3 | 130037 | 130037 | 128120 | 3 | 128799 | 10010 | 20 | 10000 | 20 | 10000 | 130037 | 130037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 129431 | 0 | 10000 | 10 | 130038 | 130038 | 130038 | 130038 | 130038 |
| 10024 | 130037 | 974 | 0 | 0 | 0 | 0 | 0 | 61 | 119540 | 25 | 10010 | 12 | 10000 | 10 | 10000 | 50 | 4660953 | 1 | 130018 | 0 | 130037 | 130037 | 128120 | 3 | 128767 | 10010 | 20 | 10000 | 20 | 10000 | 130037 | 130037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 129431 | 0 | 10000 | 10 | 130038 | 130038 | 130038 | 130038 | 130038 |
| 10024 | 130037 | 974 | 0 | 0 | 0 | 0 | 0 | 61 | 119540 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4660953 | 1 | 130018 | 0 | 130037 | 130037 | 128120 | 3 | 128767 | 10010 | 20 | 10000 | 20 | 10000 | 130037 | 130037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 2 | 0 | 3 | 1 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 129431 | 0 | 10000 | 10 | 130038 | 130038 | 130038 | 130038 | 130038 |
| 10024 | 130037 | 974 | 0 | 0 | 138 | 0 | 0 | 61 | 119540 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4660953 | 1 | 130018 | 0 | 130226 | 130225 | 128191 | 3 | 128767 | 10010 | 20 | 10000 | 20 | 10000 | 130037 | 130037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 129431 | 0 | 10000 | 10 | 130038 | 130038 | 130038 | 130038 | 130038 |
| 10024 | 130037 | 974 | 0 | 0 | 0 | 0 | 0 | 61 | 119540 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4660953 | 1 | 130018 | 0 | 130037 | 130037 | 128120 | 3 | 128767 | 10010 | 20 | 10000 | 20 | 10000 | 130037 | 130037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 129431 | 0 | 10000 | 10 | 130038 | 130038 | 130038 | 130038 | 130038 |
| 10024 | 130037 | 974 | 0 | 0 | 0 | 0 | 0 | 61 | 119540 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4660953 | 1 | 130018 | 0 | 130037 | 130037 | 128120 | 3 | 128767 | 10010 | 20 | 10000 | 20 | 10000 | 130037 | 130037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 129431 | 0 | 10000 | 10 | 130038 | 130038 | 130038 | 130038 | 130038 |
| 10024 | 130037 | 974 | 0 | 0 | 0 | 0 | 0 | 61 | 119540 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4660953 | 1 | 130018 | 0 | 130037 | 130037 | 128120 | 3 | 128767 | 10010 | 20 | 10000 | 20 | 10000 | 130037 | 130037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 129431 | 0 | 10000 | 10 | 130038 | 130038 | 130038 | 130038 | 130038 |
| 10024 | 130037 | 974 | 0 | 0 | 0 | 0 | 0 | 61 | 119540 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4660953 | 1 | 130018 | 0 | 130037 | 130037 | 128120 | 3 | 128876 | 10010 | 20 | 10000 | 20 | 10000 | 130037 | 130037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 129431 | 0 | 10000 | 10 | 130038 | 130038 | 130038 | 130038 | 130038 |
| 10024 | 130037 | 974 | 0 | 0 | 0 | 0 | 0 | 61 | 119540 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4660953 | 1 | 130018 | 0 | 130037 | 130037 | 128120 | 3 | 128767 | 10010 | 20 | 10000 | 20 | 10000 | 130037 | 130037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 129431 | 0 | 10000 | 10 | 130038 | 130038 | 130038 | 130038 | 130038 |
| 10024 | 130037 | 974 | 0 | 0 | 0 | 0 | 0 | 61 | 119540 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4660953 | 1 | 130018 | 0 | 130037 | 130037 | 128120 | 3 | 128767 | 10010 | 20 | 10000 | 20 | 10000 | 130037 | 130037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 1 | 129431 | 0 | 10000 | 10 | 130038 | 130038 | 130038 | 130038 | 130038 |
Count: 8
Code:
fsqrt v0.2d, v8.2d fsqrt v1.2d, v8.2d fsqrt v2.2d, v8.2d fsqrt v3.2d, v8.2d fsqrt v4.2d, v8.2d fsqrt v5.2d, v8.2d fsqrt v6.2d, v8.2d fsqrt v7.2d, v8.2d
movi v8.16b, 9
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 2.0006
| retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | l2 tlb miss instruction (0a) | 19 | 1e | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6b | 6d | 6e | map stall dispatch (70) | simd prf full (72) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | ld unit uop (a6) | l1d cache writeback (a8) | ac | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80204 | 160048 | 1198 | 0 | 1 | 0 | 30 | 61 | 79937 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 5677984 | 1 | 160029 | 0 | 160048 | 160048 | 149895 | 0 | 6 | 150002 | 80100 | 200 | 80008 | 200 | 80008 | 160048 | 160048 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 3 | 1 | 1 | 1 | 5117 | 1 | 16 | 1 | 1 | 159984 | 0 | 80000 | 100 | 160049 | 160049 | 160049 | 160049 | 160049 |
| 80204 | 160048 | 1199 | 1 | 1 | 0 | 0 | 61 | 79937 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 5677984 | 0 | 160264 | 0 | 160048 | 160048 | 149895 | 0 | 6 | 150002 | 80100 | 200 | 80008 | 200 | 80008 | 160048 | 160048 | 2 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 2 | 0 | 0 | 3360 | 1 | 1 | 1 | 5117 | 1 | 16 | 1 | 1 | 159984 | 0 | 80000 | 100 | 160049 | 160049 | 160049 | 160049 | 160049 |
| 80204 | 160048 | 1199 | 1 | 1 | 0 | 15 | 61 | 79937 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 5677984 | 1 | 160029 | 0 | 160048 | 160048 | 149895 | 0 | 6 | 150002 | 80100 | 200 | 80008 | 200 | 80008 | 160048 | 160048 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5117 | 1 | 16 | 1 | 1 | 159984 | 0 | 80000 | 100 | 160049 | 160049 | 160049 | 160049 | 160049 |
| 80204 | 160048 | 1199 | 1 | 1 | 0 | 0 | 61 | 79937 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 5677984 | 1 | 160029 | 0 | 160048 | 160048 | 149895 | 0 | 6 | 150002 | 80100 | 200 | 80008 | 200 | 80008 | 160048 | 160048 | 2 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5117 | 1 | 16 | 1 | 1 | 159984 | 0 | 80000 | 100 | 160049 | 160049 | 160049 | 160049 | 160049 |
| 80204 | 160048 | 1199 | 1 | 1 | 0 | 0 | 61 | 79937 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 5677984 | 1 | 160029 | 0 | 160048 | 160341 | 149895 | 0 | 6 | 150002 | 80100 | 200 | 80008 | 200 | 80008 | 160048 | 160048 | 3 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5117 | 1 | 16 | 1 | 1 | 159984 | 0 | 80000 | 100 | 160049 | 160049 | 160049 | 160049 | 160049 |
| 80204 | 160048 | 1199 | 1 | 1 | 0 | 0 | 61 | 79937 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 5677984 | 1 | 160029 | 0 | 160048 | 160048 | 149895 | 0 | 6 | 150002 | 80100 | 200 | 80072 | 200 | 80008 | 160048 | 160048 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 3 | 1 | 1 | 1 | 5117 | 1 | 16 | 1 | 1 | 159984 | 0 | 80000 | 100 | 160049 | 160049 | 160049 | 160049 | 160049 |
| 80204 | 160048 | 1199 | 1 | 1 | 0 | 822 | 61 | 79937 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 5677984 | 1 | 160029 | 0 | 160048 | 160048 | 149895 | 0 | 6 | 150002 | 80100 | 200 | 80008 | 200 | 80080 | 160048 | 160048 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5117 | 1 | 16 | 1 | 1 | 159984 | 0 | 80000 | 100 | 160049 | 160049 | 160049 | 160049 | 160049 |
| 80204 | 160048 | 1198 | 1 | 1 | 0 | 0 | 61 | 79937 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 5677984 | 1 | 160029 | 0 | 160048 | 160048 | 149895 | 0 | 6 | 150002 | 80100 | 200 | 80008 | 200 | 80080 | 160048 | 160048 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5117 | 1 | 16 | 1 | 1 | 159984 | 0 | 80000 | 100 | 160049 | 160049 | 160049 | 160049 | 160105 |
| 80204 | 160048 | 1199 | 1 | 1 | 0 | 0 | 61 | 79937 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 5677984 | 1 | 160029 | 0 | 160048 | 160048 | 149895 | 0 | 6 | 150002 | 80100 | 200 | 80008 | 200 | 80008 | 160048 | 160048 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5117 | 1 | 16 | 1 | 1 | 159984 | 0 | 80000 | 100 | 160049 | 160049 | 160049 | 160049 | 160049 |
| 80204 | 160048 | 1199 | 1 | 1 | 0 | 18 | 61 | 79921 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 5677984 | 1 | 160029 | 0 | 160048 | 160048 | 149895 | 0 | 6 | 150002 | 80100 | 200 | 80008 | 200 | 80072 | 160048 | 160048 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5117 | 1 | 16 | 1 | 1 | 159984 | 0 | 80000 | 100 | 160049 | 160049 | 160049 | 160049 | 160049 |
Result (median cycles for code divided by count): 2.0006
| retire uop (01) | cycle (02) | 03 | 1e | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d cache writeback (a8) | ac | c2 | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80024 | 160048 | 1199 | 0 | 61 | 79937 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 5677984 | 1 | 160029 | 0 | 160048 | 160048 | 149910 | 3 | 150028 | 80010 | 20 | 80000 | 20 | 80000 | 160048 | 160048 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 5020 | 14 | 16 | 12 | 12 | 159971 | 0 | 80000 | 10 | 160049 | 160049 | 160049 | 160049 | 160049 |
| 80024 | 160048 | 1198 | 0 | 61 | 79937 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 5677984 | 1 | 160029 | 0 | 160048 | 160048 | 149910 | 3 | 150028 | 80010 | 20 | 80000 | 20 | 80000 | 160048 | 160048 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 4 | 0 | 0 | 0 | 0 | 5020 | 12 | 16 | 17 | 13 | 159971 | 0 | 80000 | 10 | 160049 | 160049 | 160049 | 160107 | 160049 |
| 80024 | 160048 | 1199 | 0 | 536 | 79937 | 25 | 80027 | 10 | 80000 | 10 | 80000 | 50 | 5677984 | 1 | 160029 | 0 | 160048 | 160048 | 149910 | 3 | 150028 | 80010 | 20 | 80000 | 20 | 80000 | 160048 | 160048 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 5020 | 17 | 16 | 16 | 13 | 159971 | 2 | 80000 | 10 | 160049 | 160049 | 160049 | 160049 | 160049 |
| 80024 | 160048 | 1199 | 0 | 61 | 79937 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 5677984 | 1 | 160029 | 3 | 160048 | 160048 | 149910 | 3 | 150028 | 80010 | 20 | 80000 | 20 | 80000 | 160048 | 160048 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 5020 | 17 | 16 | 17 | 14 | 159971 | 0 | 80000 | 10 | 160049 | 160049 | 160049 | 160049 | 160049 |
| 80024 | 160048 | 1198 | 0 | 61 | 79937 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 5677984 | 1 | 160029 | 0 | 160048 | 160048 | 149910 | 3 | 150028 | 80010 | 20 | 80000 | 20 | 80000 | 160048 | 160048 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 5020 | 13 | 16 | 12 | 12 | 159971 | 0 | 80000 | 10 | 160049 | 160049 | 160049 | 160049 | 160049 |
| 80024 | 160048 | 1199 | 0 | 82 | 79937 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 5677984 | 1 | 160029 | 0 | 160048 | 160048 | 149910 | 3 | 150028 | 80010 | 20 | 80000 | 20 | 80000 | 160048 | 160107 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 183 | 0 | 0 | 0 | 5043 | 15 | 16 | 15 | 16 | 159971 | 0 | 80000 | 10 | 160049 | 160049 | 160049 | 160049 | 160049 |
| 80024 | 160048 | 1199 | 0 | 61 | 79937 | 25 | 80010 | 10 | 80017 | 10 | 80000 | 50 | 5677984 | 1 | 160029 | 0 | 160048 | 160048 | 149910 | 3 | 150028 | 80010 | 20 | 80000 | 20 | 80000 | 160048 | 160048 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 5020 | 12 | 16 | 11 | 14 | 159971 | 0 | 80000 | 10 | 160049 | 160049 | 160049 | 160049 | 160049 |
| 80024 | 160048 | 1198 | 0 | 61 | 79937 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 5677984 | 0 | 160029 | 0 | 160048 | 160048 | 149910 | 3 | 150028 | 80010 | 20 | 80000 | 20 | 80000 | 160048 | 160048 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 5020 | 11 | 16 | 13 | 17 | 160047 | 0 | 80000 | 10 | 160049 | 160049 | 160049 | 160049 | 160049 |
| 80024 | 160048 | 1199 | 0 | 61 | 79937 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 5677984 | 0 | 160029 | 0 | 160048 | 160048 | 149910 | 3 | 150028 | 80010 | 20 | 80000 | 20 | 80000 | 160048 | 160048 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 5020 | 10 | 16 | 12 | 17 | 159971 | 0 | 80000 | 10 | 160049 | 160049 | 160049 | 160049 | 160049 |
| 80024 | 160048 | 1199 | 0 | 61 | 79937 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 5677984 | 1 | 160029 | 0 | 160106 | 160048 | 149910 | 3 | 150028 | 80010 | 20 | 80000 | 20 | 80000 | 160048 | 160048 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 5020 | 16 | 16 | 14 | 16 | 159971 | 0 | 80000 | 10 | 160049 | 160049 | 160049 | 160049 | 160049 |