Firestorm: FSQRT (vector, 4H) measurements

Code:

  fsqrt v0.4h, v0.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	8037	60	0	0	61	6720	25	1000	1000	1000	281261	8018	8037	8037	7493	0	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038
1004	8037	60	0	0	61	6720	25	1000	1000	1000	281261	8018	8037	8037	7493	0	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038
1004	8037	60	6	0	61	6720	25	1000	1000	1000	281261	8018	8037	8037	7493	0	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038
1004	8037	60	108	0	61	6720	25	1000	1000	1000	281261	8018	8037	8037	7493	0	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038
1004	8037	60	351	0	61	6720	25	1000	1000	1000	281261	8018	8037	8037	7493	0	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038
1004	8037	60	0	0	61	6720	25	1000	1000	1000	281261	8018	8037	8037	7493	0	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038
1004	8037	60	0	0	61	6720	25	1000	1000	1000	281261	8018	8037	8037	7493	0	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038
1004	8037	60	0	0	61	6720	25	1000	1000	1000	281261	8018	8037	8037	7493	0	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038
1004	8037	60	0	0	61	6720	25	1000	1000	1000	281261	8018	8037	8037	7493	0	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038
1004	8037	61	282	0	61	6720	25	1000	1000	1000	281261	8018	8037	8037	7493	0	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038

Test 2: Latency 1->2

Code:

  fsqrt v0.4h, v0.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 8.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	80037	599	0	0	0	103	69720	25	10100	100	10000	100	10000	500	2864261	80018	80037	80037	78343	0	3	78745	10100	200	10000	200	10000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	79676	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	61	69720	25	10100	100	10000	100	10000	500	2864261	80018	80037	80037	78343	0	3	78745	10100	200	10000	200	10000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	79676	10000	100	80038	80072	80038	80038	80038
10204	80037	600	0	0	0	61	69720	25	10100	100	10000	100	10000	500	2864261	80018	80037	80037	78343	0	3	78745	10100	200	10000	200	10000	80037	80037	1	1	10201	100	99	100	100	10000	100	9	0	710	1	16	1	1	79676	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	61	69720	83	10100	100	10000	100	10000	500	2864261	80018	80037	80037	78343	0	3	78745	10100	200	10000	200	10000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	79676	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	61	69720	25	10100	100	10000	100	10000	500	2864261	80018	80037	80037	78343	0	3	78745	10100	200	10000	200	10000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	79676	10000	100	80038	80038	80038	80038	80038
10204	80037	600	0	0	0	82	69720	25	10100	100	10000	100	10000	500	2864261	80018	80037	80037	78343	0	3	78745	10100	200	10000	200	10000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	79676	10000	100	80038	80038	80038	80038	80038
10204	80037	600	0	0	0	1024	69720	25	10100	100	10000	100	10000	500	2864261	80018	80037	80037	78343	0	3	78745	10100	200	10000	200	10000	80037	80037	1	1	10201	100	99	100	100	10000	100	5	9	710	1	16	1	1	79676	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	61	69720	25	10100	100	10000	100	10000	500	2864261	80018	80037	80037	78343	0	3	78745	10100	200	10000	200	10000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	79676	10000	100	80038	80038	80038	80038	80038
10204	80037	600	0	0	0	251	69706	25	10100	100	10000	100	10000	500	2864261	80018	80037	80037	78343	0	3	78745	10100	200	10000	200	10000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	79676	10000	100	80038	80038	80038	80038	80038
10204	80037	600	0	0	0	251	69720	25	10100	100	10000	100	10000	500	2864261	80018	80037	80037	78343	0	3	78745	10100	200	10000	200	10000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	79676	10000	100	80038	80038	80038	80038	80038

1000 unrolls and 10 iterations

Result (median cycles for code): 8.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	80037	599	0	0	4	9	0	61	69720	25	10010	10	10000	10	10000	50	2864261	0	80018	80037	80037	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	79676	10000	10	80038	80038	80038	80038	80038
10024	80037	600	0	0	0	0	0	61	69720	25	10010	10	10000	10	10000	50	2864261	0	80018	80037	80037	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	79676	10000	10	80038	80038	80038	80038	80038
10024	80037	599	0	0	0	0	0	61	69720	25	10010	10	10000	10	10000	50	2864261	1	80018	80037	80037	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	79676	10000	10	80038	80038	80038	80038	80038
10024	80037	599	0	0	0	0	0	82	69720	25	10010	10	10000	10	10000	50	2864261	0	80018	80037	80037	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	1	640	2	16	2	2	79748	10000	10	80038	80038	80038	80038	80038
10024	80037	600	0	0	0	0	0	61	69720	25	10010	10	10000	10	10000	50	2864261	0	80018	80037	80037	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	79676	10000	10	80038	80038	80038	80038	80038
10024	80037	599	0	0	0	12	0	61	69720	25	10010	10	10000	10	10000	50	2864261	0	80018	80037	80037	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	3	3	0	0	640	2	16	2	2	79676	10000	10	80038	80038	80038	80038	80038
10024	80037	599	0	0	0	0	0	61	69720	25	10014	13	10000	10	10000	50	2864261	0	80018	80037	80037	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	79676	10000	10	80038	80038	80038	80038	80038
10024	80037	600	0	0	0	0	0	726	69720	25	10010	10	10000	10	10000	50	2864261	0	80018	80037	80037	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	79676	10000	10	80038	80038	80038	80038	80038
10024	80037	600	0	0	0	0	0	726	69720	25	10010	10	10000	10	10000	50	2864261	0	80018	80037	80037	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	79676	10000	10	80038	80038	80038	80038	80038
10024	80037	600	0	0	0	0	0	768	69720	25	10010	10	10000	10	10000	50	2864261	0	80018	80037	80037	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	79676	10000	10	80038	80038	80038	80038	80038

Test 3: throughput

Count: 8

Code:

  fsqrt v0.4h, v8.4h
  fsqrt v1.4h, v8.4h
  fsqrt v2.4h, v8.4h
  fsqrt v3.4h, v8.4h
  fsqrt v4.4h, v8.4h
  fsqrt v5.4h, v8.4h
  fsqrt v6.4h, v8.4h
  fsqrt v7.4h, v8.4h

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	st unit uop (a7)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80205	160043	1199	0	0	0	0	61	79937	25	80100	100	80000	100	80000	500	5677984	1	160024	0	160043	160043	149895	0	6	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	3	1	1	1	5117	0	16	0	0	159981	80000	100	160044	160044	160044	160044	160044
80204	160043	1199	0	1	186	0	284	79937	25	80100	100	80000	100	80000	500	5677984	1	160024	0	160043	160043	149895	0	6	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5117	0	16	0	0	159981	80000	100	160044	160044	160044	160044	160044
80204	160043	1199	0	0	0	0	61	79937	25	80100	100	80000	100	80000	500	5677984	1	160024	0	160043	160043	149895	0	6	149997	80100	200	80072	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5117	0	16	0	0	159981	80000	100	160044	160044	160044	160044	160044
80204	160043	1198	0	0	0	0	726	79937	25	80100	100	80000	100	80000	500	5677984	1	160024	0	160043	160043	149895	3	6	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5117	0	16	0	0	159981	80000	100	160044	160044	160044	160044	160044
80205	160043	1199	0	0	0	0	61	79937	25	80100	100	80000	100	80000	500	5677984	1	160024	0	160043	160043	149895	0	6	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5117	0	16	0	0	159981	80000	100	160044	160044	160044	160044	160044
80204	160043	1198	0	0	198	0	1024	79937	25	80100	100	80000	100	80000	500	5677984	1	160024	0	160043	160043	149895	0	6	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5117	0	16	0	0	159981	80000	100	160044	160044	160044	160044	160044
80204	160043	1199	0	0	0	0	61	79937	25	80100	100	80000	100	80000	500	5677984	1	160024	0	160043	160043	149895	0	6	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5117	0	16	0	0	159981	80000	100	160044	160044	160044	160044	160044
80204	160043	1198	0	0	0	0	61	79937	25	80100	100	80000	100	80000	500	5677984	1	160024	0	160043	160043	149895	0	6	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5117	0	16	0	0	159981	80000	100	160044	160044	160044	160044	160044
80204	160043	1198	0	0	0	0	61	79937	25	80100	100	80000	100	80000	500	5677984	1	160024	0	160043	160043	149895	0	6	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5117	0	16	0	0	159981	80000	100	160044	160044	160044	160044	160044
80204	160043	1198	0	0	0	0	61	79937	25	80100	100	80000	100	80000	500	5677984	1	160024	0	160043	160043	149895	0	6	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5117	0	16	0	0	159981	80000	100	160044	160044	160044	160044	160044

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	df	e0	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	160043	1199	0	2354	79937	25	80010	10	80000	10	80000	50	5677984	0	0	160024	0	160043	160043	149910	3	150023	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5022	0	0	0	17	16	0	0	7	5	2	159969	9	80000	10	160044	160044	160044	160044	160044
80024	160096	1199	0	2957	79937	25	80010	10	80000	10	80000	50	5677984	0	0	160024	0	160043	160096	149910	3	150023	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5022	0	0	0	6	16	0	0	5	5	2	159969	0	80000	10	160044	160044	160044	160044	160044
80024	160043	1199	0	848	79937	25	80010	10	80000	10	80000	50	5677984	0	0	160024	0	160043	160043	149910	3	150023	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5022	0	0	0	4	16	0	0	7	5	2	159969	0	80000	10	160044	160044	160044	160044	160044
80024	160043	1199	0	387	79937	25	80010	10	80000	10	80000	50	5677984	0	0	160024	0	160043	160043	149910	3	150023	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5022	0	0	0	5	16	0	0	6	11	2	159969	0	80000	10	160044	160044	160044	160044	160044
80024	160203	1199	0	811	79937	25	80010	10	80000	10	80000	50	5677984	0	0	160024	0	160043	160043	149910	3	150023	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5022	0	0	0	5	16	0	0	6	4	2	159969	0	80000	10	160044	160044	160044	160044	160044
80024	160043	1199	0	2959	79937	25	80010	10	80000	10	80000	50	5677984	0	0	160024	0	160043	160043	149910	3	150023	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5022	0	0	0	3	16	0	0	5	6	2	159969	0	80000	10	160044	160044	160044	160044	160044
80024	160043	1198	0	438	79937	25	80010	10	80000	10	80000	50	5677984	0	0	160024	0	160043	160043	149910	3	150023	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5022	0	2	0	3	16	0	0	4	6	2	159969	0	80000	10	160044	160044	160044	160044	160044
80024	160043	1198	0	2836	79937	25	80010	10	80000	10	80000	50	5677984	0	0	160024	0	160043	160043	149910	3	150023	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5022	0	0	0	3	16	0	0	9	5	2	159969	0	80000	10	160044	160044	160044	160044	160044
80024	160043	1198	0	550	79937	25	80010	10	80000	10	80000	50	5677984	0	0	160024	0	160043	160043	149910	3	150023	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5022	0	0	0	4	16	0	0	6	9	2	159969	0	80000	10	160044	160044	160044	160044	160044
80024	160043	1198	285	361	79937	43	80010	10	80000	10	80000	50	5677984	0	0	160024	0	160043	160043	149910	3	150023	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	69	0	0	0	0	5022	0	0	0	5	16	0	0	5	9	2	159969	0	80000	10	160044	160044	160044	160044	160044

FSQRT (vector, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations