Firestorm: FSQRT (vector, 4S) measurements

Code:

  fsqrt v0.4s, v0.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	10037	75	0	0	61	8648	25	1000	1000	1000	351941	1	10018	10037	10037	9395	3	9895	1000	1000	1000	10037	10037	1	1	1001	1000	0	0	73	1	16	1	1	9578	1000	10038	10038	10038	10038	10038
1004	10037	75	0	0	61	8648	25	1000	1000	1000	351941	0	10018	10037	10037	9395	3	9895	1000	1000	1000	10037	10037	1	1	1001	1000	0	75	73	1	16	1	1	9578	1000	10038	10038	10038	10038	10038
1004	10037	75	0	0	61	8648	25	1000	1000	1000	351941	1	10018	10037	10037	9395	3	9895	1000	1000	1000	10037	10037	1	1	1001	1000	0	0	73	1	16	1	1	9578	1000	10038	10038	10038	10038	10038
1004	10037	75	0	0	61	8648	25	1000	1000	1000	351941	1	10018	10037	10037	9395	3	9895	1000	1000	1000	10037	10037	1	1	1001	1000	0	0	73	1	16	1	1	9578	1000	10038	10038	10038	10038	10038
1004	10037	75	0	0	61	8648	25	1000	1000	1000	351941	1	10018	10037	10037	9395	3	9895	1000	1000	1000	10037	10037	1	1	1001	1000	0	45	73	1	16	1	1	9578	1000	10038	10038	10038	10038	10038
1004	10037	75	0	9	61	8648	25	1000	1000	1000	351941	1	10018	10037	10037	9395	3	9895	1000	1000	1000	10037	10037	1	1	1001	1000	0	0	73	1	16	1	1	9586	1000	10038	10038	10038	10038	10038
1004	10037	75	0	0	61	8648	25	1000	1000	1000	351941	1	10018	10037	10037	9395	3	9895	1000	1000	1000	10037	10037	1	1	1001	1000	0	0	73	1	16	1	1	9578	1000	10038	10038	10038	10038	10038
1004	10037	75	0	0	61	8648	25	1000	1000	1000	351941	1	10018	10037	10037	9395	3	9895	1000	1000	1000	10037	10037	1	1	1001	1000	0	0	73	1	16	1	1	9578	1000	10038	10038	10038	10038	10038
1004	10037	75	0	0	61	8648	25	1000	1000	1000	351941	1	10018	10037	10037	9395	3	9895	1000	1000	1000	10037	10037	1	1	1001	1000	0	60	73	1	16	1	1	9578	1000	10038	10038	10038	10038	10038
1004	10037	75	0	0	61	8648	25	1000	1000	1000	351941	1	10018	10037	10037	9395	3	9895	1000	1000	1000	10037	10037	1	1	1001	1000	0	0	73	1	16	1	1	9578	1000	10038	10038	10038	10038	10038

Test 2: Latency 1->2

Code:

  fsqrt v0.4s, v0.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	100037	749	0	0	0	61	89648	25	10100	100	10000	100	10000	500	3582941	0	100018	100037	100037	98245	3	98745	10100	200	10000	200	10000	100037	100037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	99578	0	10000	100	100086	100038	100038	100038	100038
10204	100037	749	0	0	0	61	89648	25	10100	100	10000	100	10000	500	3582941	1	100018	100037	100037	98245	3	98745	10100	200	10000	200	10000	100037	100037	1	1	10201	100	99	100	100	10000	100	0	204	0	0	0	710	1	16	1	1	99578	0	10000	100	100038	100038	100038	100038	100038
10204	100037	749	0	0	0	726	89648	25	10100	100	10000	100	10000	500	3582941	0	100018	100037	100037	98245	3	98745	10100	200	10000	200	10000	100037	100037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	99578	0	10000	100	100038	100038	100038	100038	100038
10204	100037	749	0	0	0	61	89648	25	10100	100	10000	100	10000	500	3582941	0	100018	100037	100037	98245	3	98745	10100	200	10000	200	10000	100037	100037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	99578	0	10000	100	100038	100038	100038	100038	100038
10204	100037	749	0	0	0	61	89648	25	10100	100	10000	100	10000	500	3582941	1	100018	100037	100037	98245	3	98745	10143	200	10000	200	10000	100037	100037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	17	1	1	99578	0	10000	100	100038	100038	100038	100038	100038
10204	100037	749	0	0	0	346	89648	25	10100	100	10000	100	10000	500	3582941	0	100018	100037	100037	98245	3	98745	10100	200	10000	200	10000	100037	100037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	99578	0	10000	100	100038	100038	100038	100038	100038
10204	100037	749	0	0	0	61	89648	25	10100	100	10000	100	10000	500	3582941	1	100018	100037	100037	98245	3	98745	10100	200	10000	200	10000	100037	100037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	99578	0	10000	100	100038	100038	100038	100038	100038
10204	100037	749	0	0	0	61	89648	25	10100	100	10000	100	10000	500	3582941	0	100018	100037	100037	98245	3	98745	10100	200	10000	200	10000	100037	100037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	99578	0	10000	100	100038	100038	100038	100038	100038
10204	100037	749	0	0	0	61	89648	25	10100	100	10000	100	10000	500	3582941	1	100018	100037	100037	98245	3	98745	10100	200	10000	200	10000	100037	100037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	99578	0	10000	100	100038	100038	100038	100038	100038
10204	100037	749	0	0	0	61	89648	25	10100	100	10000	100	10000	500	3582941	0	100018	100037	100037	98245	3	98745	10100	200	10000	200	10000	100037	100037	1	1	10202	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	99578	0	10000	100	100038	100038	100038	100038	100038

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	100037	749	0	0	0	0	9	0	0	61	89648	25	10010	10	10000	10	10000	50	3582941	0	100018	100037	100037	98267	3	98767	10010	20	10000	20	10000	100037	100037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	99578	0	10000	10	100038	100038	100038	100038	100038
10024	100037	750	0	0	0	0	609	0	0	61	89648	25	10010	10	10000	10	10000	50	3582941	1	100018	100037	100037	98267	3	98767	10010	20	10000	20	10000	100037	100037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	24	2	2	99578	0	10000	10	100038	100038	100038	100038	100038
10024	100037	749	0	0	0	0	0	0	0	61	89648	25	10010	10	10000	10	10000	50	3582941	0	100018	100037	100037	98267	3	98767	10010	20	10000	20	10000	100037	100037	1	1	10021	10	9	10	10	10000	10	0	0	103	6	0	1	0	640	2	16	2	2	99578	0	10000	10	100038	100038	100038	100038	100038
10024	100037	750	0	0	0	0	0	0	0	61	89648	25	10010	10	10000	10	10000	50	3582941	0	100018	100037	100037	98267	3	98767	10010	20	10000	20	10000	100037	100037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	99578	0	10000	10	100038	100038	100038	100038	100038
10024	100037	749	0	0	0	0	0	0	0	61	89648	25	10010	10	10000	10	10000	50	3582941	0	100018	100037	100037	98267	3	98767	10010	20	10000	20	10000	100037	100037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	99578	0	10000	10	100038	100038	100038	100081	100038
10024	100037	749	0	0	0	0	0	0	0	61	89648	25	10010	10	10000	10	10000	50	3582941	0	100018	100037	100037	98267	3	98767	10010	20	10000	20	10000	100037	100037	2	1	10021	10	9	10	10	10000	10	0	0	0	3	0	0	0	640	2	16	2	2	99578	0	10000	10	100038	100038	100038	100038	100038
10024	100037	749	0	0	0	0	6	0	0	61	89648	25	10010	10	10000	10	10000	50	3582941	0	100018	100037	100037	98267	3	98767	10010	20	10000	20	10000	100037	100037	1	1	10021	10	9	10	10	10000	10	0	0	7	0	0	0	0	640	2	16	2	2	99578	0	10000	10	100038	100038	100038	100038	100038
10024	100037	749	0	0	0	0	0	0	0	61	89648	25	10010	10	10000	10	10000	50	3582941	0	100018	100037	100037	98267	3	98767	10010	20	10000	20	10000	100037	100037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	99578	0	10000	10	100038	100038	100038	100038	100038
10024	100037	750	0	0	0	0	0	0	0	61	89648	25	10010	10	10000	10	10000	50	3582941	0	100018	100037	100037	98267	3	98767	10010	20	10000	20	10000	100037	100037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	99578	0	10000	10	100038	100038	100038	100038	100038
10024	100037	749	0	0	0	0	0	0	0	61	89648	25	10010	10	10000	10	10000	50	3582941	0	100018	100037	100037	98267	3	98767	10010	20	10000	20	10000	100037	100037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	99578	0	10000	10	100038	100038	100038	100038	100038

Test 3: throughput

Count: 8

Code:

  fsqrt v0.4s, v8.4s
  fsqrt v1.4s, v8.4s
  fsqrt v2.4s, v8.4s
  fsqrt v3.4s, v8.4s
  fsqrt v4.4s, v8.4s
  fsqrt v5.4s, v8.4s
  fsqrt v6.4s, v8.4s
  fsqrt v7.4s, v8.4s

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	160045	1199	0	0	61	79937	25	80100	100	80000	100	80000	500	5677984	1	160026	0	160045	160045	149895	0	6	149999	80100	200	80072	200	80008	160045	160045	1	1	80201	100	99	100	100	80000	100	0	31	0	0	0	1	1	1	5117	0	16	0	0	159981	0	80000	100	160046	160046	160046	160046	160046
80204	160045	1199	0	0	542	79937	25	80100	100	80000	100	80000	511	5677984	1	160026	0	160045	160045	149895	0	6	149999	80100	200	80008	200	80008	160045	160045	1	1	80201	100	99	100	100	80000	100	0	123	0	0	0	1	1	1	5117	0	16	0	0	159981	0	80000	100	160046	160046	160046	160046	160046
80204	160045	1198	0	0	61	79937	25	80100	100	80000	100	80000	500	5677984	1	160026	0	160045	160045	149895	0	6	149999	80100	200	80008	200	80008	160045	160045	1	1	80201	100	99	100	100	80000	100	0	40	0	0	2	1	1	1	5117	0	16	0	0	160076	0	80000	100	160046	160046	160046	160046	160046
80204	160375	1199	0	30	103	79937	25	80100	100	80000	100	80000	500	5677984	1	160026	0	160045	160045	149895	0	6	149999	80100	200	80008	200	80008	160045	160045	1	1	80201	100	99	100	100	80000	100	0	95	0	0	0	1	1	1	5117	0	16	0	0	159981	0	80000	100	160046	160046	160046	160046	160046
80204	160045	1199	0	0	61	79937	25	80100	100	80000	100	80000	500	5677984	1	160026	0	160045	160045	149895	0	6	149999	80100	200	80008	200	80008	160045	160100	1	1	80201	100	99	100	100	80000	100	0	7	0	0	0	1	1	1	5117	0	16	0	0	159981	0	80000	100	160046	160046	160046	160046	160046
80204	160045	1199	0	0	61	79937	25	80100	100	80000	100	80000	500	5677984	1	160026	0	160045	160045	149927	0	6	149999	80100	200	80008	200	80008	160045	160045	1	1	80201	100	99	100	100	80000	100	0	3	0	3	0	1	1	1	5117	0	17	0	0	159981	0	80000	100	160046	160046	160046	160046	160046
80204	160045	1199	0	0	726	79937	25	80100	100	80016	100	80000	500	5677984	1	160026	0	160045	160045	149895	0	6	149999	80156	200	80008	200	80008	160045	160045	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	1	1	1	5117	0	16	0	0	159981	0	80000	100	160046	160046	160046	160046	160046
80204	160045	1199	0	0	61	79937	25	80100	100	80000	100	80000	500	5677984	1	160026	0	160045	160045	149895	0	6	149999	80100	200	80008	200	80008	160045	160045	1	1	80201	100	99	100	100	80000	100	0	0	0	9	0	1	1	1	5117	0	16	0	0	160037	0	80000	100	160046	160046	160100	160046	160046
80204	160045	1198	0	12	726	79937	25	80100	100	80000	100	80000	500	5677984	1	160026	0	160045	160045	149895	0	6	149999	80100	200	80008	200	80008	160045	160045	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	1	1	1	5117	0	16	0	0	159981	0	80000	100	160046	160046	160046	160046	160046
80204	160045	1199	0	0	124	79937	25	80100	100	80000	100	80000	500	5677984	1	160026	0	160045	160045	149895	0	6	150045	80100	200	80008	200	80008	160045	160045	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	1	1	1	5117	0	16	0	0	159981	0	80000	100	160046	160046	160046	160046	160046

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	160045	1198	0	0	61	79937	25	80010	10	80000	10	80144	50	5677984	160026	160045	160045	149910	3	150025	80010	20	80358	20	80000	160045	160045	1	1	80021	10	9	10	10	80000	10	2	2	2	0	0	2	0	0	5037	21	16	11	6	159972	108	0	80000	10	160046	160046	160046	160046	160046
80024	160045	1199	0	0	61	79937	25	80010	10	80000	10	80000	50	5677984	160026	160045	160045	149910	3	150025	80010	20	80000	20	80000	160045	160045	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	5	16	9	10	159972	93	0	80000	10	160046	160046	160046	160046	160046
80024	160045	1198	0	0	61	79937	25	80010	10	80000	10	80000	50	5677984	160026	160045	160045	149910	3	150025	80010	20	80000	20	80000	160045	160045	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	10	16	5	8	159972	77	0	80000	10	160046	160046	160046	160046	160046
80024	160045	1199	0	0	61	79937	25	80010	10	80000	10	80000	50	5677984	160026	160045	160045	149910	3	150025	80010	20	80000	20	80000	160045	160045	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	4	16	8	6	159972	77	0	80000	10	160046	160046	160046	160046	160046
80024	160045	1199	0	0	61	79937	25	80010	10	80000	10	80000	50	5677984	160026	160045	160100	149910	3	150025	80010	20	80000	20	80000	160045	160045	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	8	16	7	6	159972	93	0	80000	10	160046	160046	160046	160046	160046
80024	160045	1199	0	0	61	79937	25	80010	10	80000	10	80000	50	5677984	160026	160045	160045	149910	3	150025	80010	20	80000	20	80000	160045	160045	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	11	16	6	4	159972	93	0	80000	10	160046	160046	160046	160046	160046
80024	160045	1198	0	0	61	79937	25	80010	10	80000	10	80000	50	5677984	160026	160045	160045	149910	3	150025	80010	20	80000	20	80000	160045	160045	1	1	80021	10	9	10	10	80000	10	0	0	0	0	27	0	0	0	5020	8	16	7	15	159972	77	0	80000	10	160046	160046	160046	160046	160046
80024	160045	1199	30	0	61	79937	25	80010	10	80000	10	80000	50	5677984	160026	160045	160045	149910	3	150025	80010	20	80000	20	80000	160045	160045	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	5	16	7	10	159972	77	0	80000	10	160046	160046	160046	160046	160046
80024	160045	1199	0	0	61	79937	25	80010	10	80000	10	80000	50	5677984	160026	160045	160045	149910	3	150025	80010	20	80000	20	80000	160045	160045	1	1	80021	10	9	10	10	80000	10	0	0	0	0	201	0	0	0	5020	9	16	6	8	159972	77	0	80000	10	160046	160046	160046	160046	160046
80024	160045	1199	0	0	61	79937	25	80010	10	80000	10	80000	50	5677984	160026	160045	160045	149910	3	150025	80010	20	80000	20	80000	160045	160045	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	7	16	14	11	159972	93	0	80000	10	160046	160046	160046	160046	160046

FSQRT (vector, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations