Firestorm: FSQRT (vector, 8H) measurements

Code:

  fsqrt v0.8h, v0.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	8037	60	0	0	0	61	6720	25	1000	1000	1000	281261	1	8018	8037	8037	7493	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	0	0	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038
1004	8037	60	0	0	0	61	6720	25	1000	1000	1000	281261	1	8018	8037	8037	7493	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	0	0	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038
1004	8037	60	0	0	0	61	6720	25	1000	1000	1000	281261	0	8018	8037	8037	7493	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	0	0	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038
1004	8037	60	0	1	12	61	6720	25	1000	1000	1000	281261	0	8018	8037	8037	7493	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	0	0	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038
1004	8037	60	0	0	0	61	6720	25	1000	1000	1000	281261	1	8018	8037	8037	7493	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	0	57	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038
1004	8037	60	0	0	0	61	6720	25	1000	1000	1000	281261	1	8018	8037	8037	7493	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	0	0	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038
1004	8037	61	0	0	0	61	6720	25	1000	1000	1000	281261	1	8018	8037	8037	7493	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	0	0	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038
1004	8037	60	0	0	0	61	6720	25	1000	1000	1000	281261	1	8018	8037	8037	7493	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	0	0	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038
1004	8037	61	1	0	0	61	6720	25	1000	1000	1000	281261	1	8018	8037	8037	7493	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	0	0	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038
1004	8037	60	0	0	0	61	6720	25	1000	1000	1000	281261	1	8018	8037	8037	7493	3	7895	1000	1000	1000	8037	8037	1	1	1001	1000	0	0	73	1	16	1	1	7676	1000	8038	8038	8038	8038	8038

Test 2: Latency 1->2

Code:

  fsqrt v0.8h, v0.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 8.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	80037	600	0	0	0	0	408	61	69720	25	10100	100	10000	100	10000	500	2864261	0	80018	80037	80037	78343	3	78745	10100	200	10000	200	10000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	79676	0	10000	100	80038	80038	80038	80038	80038
10204	80037	600	0	0	0	0	39	61	69720	25	10100	100	10000	100	10000	500	2864261	1	80018	80037	80037	78343	3	78745	10100	200	10000	200	10000	80037	80037	1	1	10201	100	99	100	100	10000	100	2	0	0	0	710	1	16	1	1	79676	0	10000	100	80038	80038	80038	80038	80038
10204	80037	600	0	0	0	0	51	61	69720	25	10100	100	10000	100	10000	500	2864261	0	80018	80037	80037	78343	3	78745	10100	200	10000	200	10000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	79676	0	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	0	21	61	69720	25	10100	100	10000	100	10000	500	2864261	0	80018	80037	80037	78343	3	78745	10100	200	10000	200	10000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	79676	0	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	0	18	103	69720	25	10100	100	10000	100	10000	500	2864261	1	80018	80037	80037	78343	3	78745	10100	200	10000	200	10000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	3	710	1	16	1	1	79676	0	10000	100	80038	80038	80038	80038	80038
10204	80131	600	1	1	2	2	495	61	69720	25	10100	100	10000	100	10000	500	2864261	0	80018	80037	80037	78343	3	78745	10100	200	10000	200	10000	80037	80037	1	1	10202	100	99	100	100	10000	100	0	0	1	0	710	1	16	1	1	79676	0	10000	100	80038	80038	80038	80038	80038
10204	80037	600	0	0	0	0	360	126	69720	25	10100	100	10000	100	10000	516	2864563	0	80018	80037	80037	78343	3	78745	10222	200	10000	200	10000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	2	0	0	710	1	16	1	1	79676	0	10000	100	80038	80038	80038	80038	80038
10204	80037	600	0	0	0	0	84	61	69720	25	10100	100	10000	100	10000	500	2864261	0	80018	80037	80037	78343	3	78745	10100	200	10000	200	10000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	79676	0	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	0	192	61	69720	25	10100	100	10000	100	10000	500	2864261	0	80053	80037	80037	78343	3	78745	10100	200	10000	200	10000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	79676	0	10000	100	80038	80038	80038	80038	80038
10204	80037	600	0	0	0	0	468	82	69720	25	10100	111	10000	100	10000	500	2864261	0	80018	80037	80037	78343	3	78745	10100	200	10000	200	10000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	0	16	1	1	79676	0	10000	100	80038	80038	80038	80038	80038

1000 unrolls and 10 iterations

Result (median cycles for code): 8.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	80037	599	0	54	61	69720	25	10010	10	10000	10	10000	50	2864261	80018	80037	80037	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	1	0	640	2	16	2	2	79676	10000	10	80038	80038	80038	80038	80038
10024	80037	599	0	51	61	69720	25	10010	10	10000	10	10000	50	2864261	80018	80037	80037	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	79676	10000	10	80038	80038	80038	80038	80038
10024	80037	600	0	30	61	69720	25	10010	10	10000	10	10000	50	2864261	80018	80037	80037	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	79676	10000	10	80038	80038	80038	80038	80038
10024	80037	600	0	33	61	69720	25	10010	10	10000	10	10000	50	2864261	80018	80037	80037	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	79676	10000	10	80038	80038	80038	80038	80038
10024	80037	599	0	36	61	69720	25	10010	10	10000	10	10000	50	2864261	80018	80037	80037	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	79676	10000	10	80038	80038	80038	80038	80038
10024	80037	599	0	0	61	69720	25	10010	10	10000	10	10000	50	2864261	80018	80037	80037	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	79676	10000	10	80038	80038	80038	80038	80038
10024	80037	599	0	36	61	69720	25	10010	10	10000	10	10000	50	2864261	80018	80037	80037	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	79676	10000	10	80038	80038	80038	80071	80038
10024	80037	600	0	30	61	69720	64	10025	12	10000	10	10000	50	2864261	80018	80037	80083	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	2	2	0	0	0	0	640	2	16	2	2	79676	10000	10	80038	80038	80038	80038	80038
10024	80037	599	0	27	61	69720	25	10010	10	10000	10	10000	50	2864261	80018	80037	80037	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	79676	10000	10	80038	80038	80038	80038	80038
10024	80037	600	0	39	61	69720	25	10010	10	10000	10	10000	50	2864261	80018	80037	80037	78365	3	78767	10010	20	10000	20	10000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	79676	10000	10	80038	80038	80038	80038	80038

Test 3: throughput

Count: 8

Code:

  fsqrt v0.8h, v8.8h
  fsqrt v1.8h, v8.8h
  fsqrt v2.8h, v8.8h
  fsqrt v3.8h, v8.8h
  fsqrt v4.8h, v8.8h
  fsqrt v5.8h, v8.8h
  fsqrt v6.8h, v8.8h
  fsqrt v7.8h, v8.8h

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3f	4e	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	160043	1199	1	1	0	61	79937	0	25	80100	100	80000	100	80000	500	5677984	0	160024	0	160043	160043	149895	0	6	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5117	0	16	1	1	159984	80000	100	160044	160044	160044	160044	160044
80204	160043	1199	1	1	0	61	79937	160027	25	80100	100	80000	100	80000	500	5677984	0	160024	0	160043	160043	149895	0	6	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5117	1	16	1	1	159984	80000	100	160044	160097	160044	160044	160044
80204	160043	1199	1	1	0	726	79937	0	25	80100	100	80015	100	80000	500	5677984	0	160024	0	160043	160043	149895	0	6	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5117	1	16	1	1	159984	80000	100	160044	160044	160044	160044	160044
80204	160043	1198	1	1	0	61	79937	0	25	80100	100	80000	100	80000	500	5677984	0	160024	0	160043	160043	149895	0	6	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5117	1	16	1	1	159984	80000	100	160044	160044	160044	160044	160044
80204	160043	1199	1	1	0	61	79937	0	25	80100	100	80000	100	80000	500	5677984	0	160024	0	160043	160043	149895	0	25	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5117	1	16	1	1	159984	80000	100	160044	160044	160044	160044	160044
80204	160043	1198	1	1	0	61	79937	0	25	80100	119	80000	100	80000	500	5677984	0	160024	0	160043	160043	149895	0	6	149997	80100	200	80008	200	80008	160043	160096	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5117	1	16	1	1	159984	80000	100	160044	160044	160044	160044	160044
80204	160043	1199	1	1	0	61	79937	0	25	80100	100	80000	100	80000	500	5677984	0	160024	0	160043	160043	149895	0	6	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5117	1	16	1	1	159984	80000	100	160044	160044	160044	160044	160044
80204	160043	1199	1	1	0	61	79937	0	25	80100	100	80000	100	80000	500	5677984	0	160024	0	160043	160043	149895	0	6	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5117	1	16	1	1	159984	80000	100	160044	160044	160044	160044	160044
80204	160043	1199	1	1	0	61	79937	0	40	80100	100	80000	100	80000	500	5677984	0	160024	0	160043	160043	149895	0	6	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5117	1	16	1	1	159984	80000	100	160044	160044	160044	160044	160044
80204	160043	1199	1	1	0	183	79937	0	25	80100	100	80000	100	80000	500	5677984	0	160024	0	160043	160043	149895	3	6	149997	80100	200	80008	200	80008	160043	160043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5130	1	16	1	1	159984	80000	100	160044	160044	160044	160044	160044

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	160043	1198	0	0	0	0	61	79937	25	80010	10	80000	10	80000	50	5677984	1	160024	0	160043	160043	149910	0	3	150023	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	10	16	0	11	15	159969	80000	10	160044	160044	160044	160044	160044
80024	160043	1200	0	0	0	0	726	79937	25	80010	10	80000	10	80000	50	5677984	1	160024	0	160043	160043	149910	0	3	150023	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	12	16	0	14	16	159969	80000	10	160044	160044	160044	160044	160044
80024	160043	1198	0	0	0	0	61	79937	25	80010	10	80000	10	80000	50	5677984	1	160077	0	160043	160043	149910	0	3	150023	80010	20	80000	20	80068	160043	160043	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	18	16	0	16	13	159969	80000	10	160044	160044	160044	160044	160044
80024	160043	1199	0	0	0	0	726	79937	25	80010	10	80000	10	80000	50	5677984	1	160024	0	160043	160043	149910	0	3	150023	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	11	16	0	10	15	159969	80000	10	160044	160044	160044	160044	160044
80025	160043	1198	0	0	0	0	1029	79937	25	80010	10	80000	10	80000	50	5677984	1	160024	0	160043	160043	149910	0	3	150023	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	12	16	0	14	15	159969	80000	10	160044	160044	160044	160044	160044
80024	160043	1199	0	0	0	0	726	79937	25	80010	10	80000	10	80000	50	5677984	1	160024	0	160043	160043	149910	0	3	150023	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	14	16	0	13	13	159969	80000	10	160044	160044	160044	160044	160044
80024	160043	1199	0	0	0	0	94	79937	25	80010	10	80000	10	80000	50	5677984	1	160024	0	160043	160043	149910	0	3	150023	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	12	16	0	11	13	159969	80000	10	160044	160044	160044	160044	160044
80024	160043	1199	0	0	0	0	726	79937	43	80010	10	80000	10	80000	50	5677984	1	160024	0	160043	160043	149910	0	3	150023	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	14	16	0	12	10	159969	80000	10	160044	160044	160044	160044	160044
80024	160043	1220	0	0	0	0	61	79937	25	80040	10	80045	10	80000	50	5677984	1	160024	0	160043	160043	149910	0	3	150023	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	16	16	0	15	15	159969	80000	10	160044	160044	160044	160044	160044
80024	160043	1199	0	0	0	0	631	79937	25	80010	10	80000	10	80000	50	5677984	1	160024	0	160043	160043	149910	0	3	150023	80010	20	80000	20	80000	160043	160043	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	13	16	0	13	13	159969	80000	10	160044	160044	160044	160044	160044

FSQRT (vector, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations