Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FSUB (scalar, D)

Test 1: uops

Code:

  fsub d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000373116112630100030383038303830383038
1004303722121032548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037220612548251000100010003983133018303730372415328951000100020003037303711100110003073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110001073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372301032548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000373116112630100030383038303830383038
10043037220612548251000100010003983133018303730372415328951000100020003037303711100110001073116112630100030383038303830383038
100430372302512548251000100010003983133018303730372415328951000100020003037303711100110001073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  fsub d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372240006129548251010010010000100100005004277313130018300373003728265032874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313130018300373003728265032874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383021930038
102043003722500063129548251010010010000100100005004277313130018300373003728265032874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313130018300373003728265032874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313130018300373003728265032874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313130018300823003728265032874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313130018300373003728265032874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313130018300373003728265032874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313130018300373003728265032874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
10204300372250008429548251010010010000100100005004277313130018300373003728265032874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500765295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830083
100243003722400170295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
100243003722400214295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630210000103003830038300383003830038
100243003722500955295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
100243003722500235295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
100243003722500214295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
100243003722500103295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
100243003722500189295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
100243003722500126295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
100253003722500170295482510010101000010100005042773131300183003730037282873287671001020101722020000300373003711100211091010100001006402162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  fsub d0, d1, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225010329548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
1020430037225014929548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
1020430037225017029548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100006071011611296340100001003003830038300383003830038
10204300372250170295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000710116112963428100001003003830038300383003830038
1020430037225014529548451010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
1020430037224014929548251010010010000100100005004277313030018300373003728265328764101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
1020430037225096129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100003071011611296340100001003003830038300383003830038
1020430037225014929548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250147295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000710116112963418100001003003830038300383003830038
1020430037225014529548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250277295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372250189295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
1002430037225082295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001036402162229630010000103003830038300383003830038
10024300372250147295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372250126295482510010101000810101495042773130300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372250126295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372250231295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
1002430037225084295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372250170295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  fsub d0, d8, d9
  fsub d1, d8, d9
  fsub d2, d8, d9
  fsub d3, d8, d9
  fsub d4, d8, d9
  fsub d5, d8, d9
  fsub d6, d8, d9
  fsub d7, d8, d9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)1e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200391500004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000030051102161120036800001002004020040200402004020040
802042003915000041258010010080000100800005006400000200202003920039997331002380221200800002021600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020195
802042003915000052625801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040
802042003915000026425801001008019210080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040
802042003915000050525801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040
802042003915000054625801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040
802042003915000047225801001008000010080000609640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040
802042003915000051425801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000051281161120036800001002004020040200402004020040
802042003915000050025801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040
802042003915000042125801001008000010080000500640000120020200392003999733999780100200800002001600002003920189118020110099100100800001000000051101161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391501100002892580010108000013801055064000001200202003920093999631001980010208000020160000200392003911800211091010800001020502400231600029182003600080000102004020040200402004020040
8002420039150110004523392580010108000010800005064000001200202003920039999631001980010208010520160000200392003911800211091010800001000502400161600029152003630080000102004020040200402009020040
80024200391501101102682580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000502400161600016182003600080000102004020040200402004020040
800242003915011000027122580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000502400151600018192012000080000102004020040200402004020040
800242003915011000321122580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001011911502400161600016162003600080000102004020040200402004020040
800242003915011000021102580010108000010800005064000001200202003920039999631001980010208000020160632200392003911800211091010800001023502400171600016162003600080000102004020040200402004020040
800242003915011000021562580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000502400171600031152003600080000102004020040200402004020040
800242003915011000022372580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000502400151600019162003600080000102004020040200402004020040
80024200391501110002702580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000502400171600027152003600080000102004020040200402004020040
800242003915011000021732580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001033502400141600023162003600680000102004020040200402004020040