Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FSUB (scalar, H)

Test 1: uops

Code:

  fsub h0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110003073216222630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110001073216222630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000373216222630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110003073216222630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000373216222630100030383038303830383038
1004303723020025482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100020003037303711100110000073216222630100030383038303830383038

Test 2: Latency 1->2

Code:

  fsub h0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722503006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250195072629548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250606129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250906129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003721102011009910010010000100000071011611296340100001003003830038300383003830038
1020430037225025506129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250360084295392510100100100001001000050042773131300543003730037282653287451010020010000200200003003730037111020110099100100100001000130710116112963421100001003003830038301333008630038
1020430084225117106129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
102043003722401206129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
102043003722401206129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300843003711102011009910010010000100009171011612296340100001003003830038300853008530038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225001200612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250018006129548251001010100001010000504277313030018300373003728287162876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037226009007262954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037225003300612952725100101010000101000050427731303001830037300372828732876710010201000020200003003730037311002110910101000010000640216222963010000103003830038300383003830038
10024300372250041400612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037311002110910101000010200640216222963010000103003830038300383003830038
10024300372250045900612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037225003300612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037225001500612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010030640216222963010000103003830038300383003830038
10024300372250027000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250040800612954825100261010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000723216222963010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  fsub h0, h1, h0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250021061295482510100100100001001000050042773133001830037300372826532874410125200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250021061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037224000061295482510100100100001001000050042773133002130037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372240039061295482510125125100001251000054142773133001830037300372826532874510100200100002002000030037300371110202100991001001000010000071011611296340100001003003830038300383003830038
1020430037225006061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037224100061295482510125125100001251000050042773133001830037300372826532876310100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100120071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500990061295482510018101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001016402162229630010000103003830038300383003830038
10024300372250000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372250000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
100243003722540270061295482510010101000010100005042773130300183003730037282873287671001020101612020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372250000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383012130038
10024300372250013501776295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372250000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
100243003722500120061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372250000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001006402164229630210000103008530038300383003830038
10024300372250116217601432295394410019101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  fsub h0, h8, h9
  fsub h1, h8, h9
  fsub h2, h8, h9
  fsub h3, h8, h9
  fsub h4, h8, h9
  fsub h5, h8, h9
  fsub h6, h8, h9
  fsub h7, h8, h9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200581511133247258010010080000100800005006400000020020200392003999733999780100200800002001600002003920039118020110099100100800001000051140121611920036800001002004020040200402004020040
802042003915011024725801001008000010080000500640000002002020039200399973399978010020080000200160000200392003911802011009910010080000100005114091691120036800001002004020040200402004020040
80204200391501102472580100100800001008000050064000000200202003920039997339997801002008000020016000020039200391180201100991001008000010000511409169920036800001002004020040200402004020040
80204200391501102472580100100800001008000050064000000200202003920039997339997801002008000020016000020039200391180201100991001008000010000511404169720036800001002004020040200402004020040
802042003915011024725801001008000010080000500640000002002020039200399973399978010020080000200160000200392003911802011009910010080000100005114511169920036800001002004020040200402004020040
80204200391501102472580100100800001008000050064000005200202003920039997339997801002008000020016000020039200391180201100991001008000010000511409169920036800001002004020040200402004020040
80204200391501102472580100100800001008000050064000005200202003920039997339997801002008000020016000020039200391180201100991001008000010000511459169920036800001002004020040200402004020040
80204200391501102472580100100800001008000050064000015200202003920039997339997801002008000020016000020039200391180201100991001008000010000511459169420036800001002004020040200402004020040
80204200391501102472580100100800001008000050064000010200202003920039997339997801002008000020016000020039200391180201100991001008000010000511409169420036800001002004020040200402004020040
8020420039150111524725801001008000010080000500640000102002020039200399973399978010020080000200160000200392003911802011009910010080000100005114591611920036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039150000018040258001010800001080000506400001200200200392003999963100198001020800002016000020039200391180021109101080000100000005020316332003680000102004020040200402004020040
800242003915000000040258001010800001080000506400001200200200392003999963100198001020800002016000020039200391180021109101080000100000005020316332003680000102004020040200402004020040
800242003915000009040258001010800001080000506400001200200200392003999963100198001020800002016000020039200391180021109101080000100000005020316232003680000102004020040200402004020040
8002420039150000000402580010108000010800005064000012002002003920039100123100198001020800002016000020039200391180021109101080000100000005020316332003680000102004020040200402004020040
800242003915000009040258001010800001080000506400001200200200392003999963100198001020800002016000020039200391180021109101080000100000005020316322003680000102004020040200402004020040
800242003915000000040258001010800001080000506400001200200200392003999963100198001020800002016000020039200391180021109101080000100004005020316322003680000102004020040200402004020040
800242003915000000040258001010800001080000506400001200200200392003999963100198001020800002016000020039200391180021109101080000100000005020316322003680000102004020040200402004020040
800242003915000000040258001010800001080000506400001200200200392003999963100198001020800002016000020039200391180021109101080000100000005020316232003680000102004020040200402004020040
800242003915000000040258001010800001080000506400001200200200392003999963100198001020800002016000020039200391180021109101080000100000005020316232003680000102004020040200402004020040
800242003915000000040258001010800001080000506400001200200200392003999963100198001020800002016000020039200391180021109101080000100000005020316332003680000102004020040200402004020040