Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FSUB (vector, 4H)

Test 1: uops

Code:

  fsub v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372406125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100020003037303711100110000373116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723084254825100010001000398313030183037303724153289510001000200030373037111001100001573116112630100030383038303830383038
100430372308425482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  fsub v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l1i tlb fill (04)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225096129548651010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001001007101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037224006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100307101161129634100001003003830038300383003830038
1020430037225006129548251014010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100107101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225006129548251010010010000102100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372240061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372250061295484310010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
100243003722512061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372240061295484510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  fsub v0.4h, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000612954825101001001000010010000500427731303001803003730037282650328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303001803003730037282650328745101002001000020020000300373003711102011009910010010000100000071011631296340100001003003830038300383003830038
102043003722510006129548251010010010000100100005004277313030018030037300372826503287451010020010000200200003003730037111020110099100100100001000412071011611296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303001803003730037282650328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
102043003722500006129548251010010010000100100005004277313030018030037300372826503287451010020010000200200003003730037111020110099100100100001000018071011611296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303001803003730037282650328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372240000612954825101001001000010010000500427731303001803003730037282650328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303003703003730037282650328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303001803003730037282650328745101002001000020020000300373003711102011009910010010000100000071011610296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303001803003730037282650328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010200640216222963010000103003830038300383003830038
10024300372240612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222969910000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  fsub v0.4h, v8.4h, v9.4h
  fsub v1.4h, v8.4h, v9.4h
  fsub v2.4h, v8.4h, v9.4h
  fsub v3.4h, v8.4h, v9.4h
  fsub v4.4h, v8.4h, v9.4h
  fsub v5.4h, v8.4h, v9.4h
  fsub v6.4h, v8.4h, v9.4h
  fsub v7.4h, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200391500000516258010010080000100800005006400002002020039200399973399978010020080000200160000200392003911802011009910010080000100010051104163320036800001002004020040200402004020040
8020420039150000041258010010080000100800005006400002002020039200399973399978010020080000200160000201122003921802011009910010080000100000051103162320036800001002004020040200402004020040
8020420039150000041258010010080000100800005006400002002020039200399973399978010020080000200160000200392003911802011009910010080000100000151102162320036800001002004020040200402004020040
8020420039150000041258010010080000100800005006400002002020039200399973399978010020080000200160000200392003911802011009910010080000100000051103162320036800001002004020040200402004020040
80204200391500000706258010010080000100800005006400002002020039200399973399978010020080000200160000200392003911802011009910010080000100000051103163320036800001002004020040200402004020040
8020420039150000041258010010080000100800005006400002002020039200399973399978010020080000200160000200392003911802011009910010080000100010051103162320036800001002004020040200402009220040
8020420039150000041258010010080000100800005006400002002020039200399973399978010020080000200160000200392003911802011009910010080000100010051102163320036800001002004020040200402004020040
8020420039150000041258010010080000100800005006400002002020039200399973399978010020080000200160000200392003911802011009910010080000100003051103162320036800001002004020040200402004020040
8020420039150000041258010010080000100800005006400002002020039200399973399978010020080000200160000200392003911802011009910010080000100000051102163220036800001002004020040200402004020040
8020420039155040041258010010080000100800005006400002002020039200399973399978010020080000200160000200392003911802011009910010080000100000051103163220036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481510006125800101080000108000050640000200202003920039999631001980010208000020160000200392003911800211091010800001000000050205164320036080000102004020040200402004020040
80024200391500004025800101080000108000050640000200202003920039999631001980010208000020160000200392003911800211091010800001000000050203163520036080000102004020040200402004020040
80024200391500006325800101080000108000050640000200202003920039999631001980010208000020160000200392003911800211091010800001000003050205165420036080000102004020040200402004020040
80024200391500104025800101080000108000050640000200202003920039999631001980010208000020160000200392003911800211091010800001000000050203163520036080000102004020040200402004020040
80024200391503006325800101080000108000050640000200202003920039999631001980010208000020160000200392003911800211091010800001000000050203163520036080000102004020040200402004020040
80024200391500004025800101080000108000050640000200202003920039999631001980010208000020160000200392003911800211091010800001000000050205163520036080000102004020040200402004020040
80024200391500004025800101080000108000050640000200202003920039999631001980010208000020160000200392003911800211091010800001000000050205165520036380000102004020040200402004020040
80024200391500004025800101080000108000050640000200202003920039999631001980010208000020160000200392003911800211091010800001000000050205163520036080000102004020040200402004020040
800242003915000124025800101080000108000050640000200202003920039999631001980010208000020160000200392003911800211091010800001000000050205164320036080000102004020040200402004020040
80024200391500004025800101080000108000050640000200202003920039999631001980010208000020160000200392003911800211091010800001000000050205163520036080000102004020040200402004020040