Firestorm: INS (element, B) measurements

Code:

  ins v0.b[2], v1.b[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	0	192	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	3	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	2	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	100	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	3	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	3	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	103	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  ins v0.b[2], v1.b[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	51	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	202	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	42	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	149	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	84	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	381	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	27	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	12	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	45	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  ins v0.b[2], v0.b[1]

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	18	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	1	1	0	21	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	722	3	24	3	3	19787	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	97	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	718	1	16	1	1	19804	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	1	0	0	1	118	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	722	3	24	3	3	19787	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	1	0	24	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	717	1	16	1	1	19804	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	1	4	12	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	3	1	0	1	1	1	717	1	16	1	1	19804	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	1	0	0	0	71	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	717	1	16	1	1	19805	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	1	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	717	1	16	1	1	19805	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	1	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	717	1	16	1	1	19805	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	1	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	718	1	16	1	1	19804	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	1	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	2070	1	1	1	718	1	16	1	1	19805	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	3f	4e	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	15	61	19686	0	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19686	0	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10167	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19686	0	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	369	61	19686	0	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19686	0	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19686	0	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	3	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19686	0	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19686	0	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19686	0	25	10010	10	10000	12	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19686	0	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  ins v0.b[2], v8.b[1]
  movi v1.16b, 0
  ins v1.b[2], v8.b[1]
  movi v2.16b, 0
  ins v2.b[2], v8.b[1]
  movi v3.16b, 0
  ins v3.b[2], v8.b[1]
  movi v4.16b, 0
  ins v4.b[2], v8.b[1]
  movi v5.16b, 0
  ins v5.b[2], v8.b[1]
  movi v6.16b, 0
  ins v6.b[2], v8.b[1]
  movi v7.16b, 0
  ins v7.b[2], v8.b[1]

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2510

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20088	150	0	0	29	25	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10120	2	16	1	2	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	694	25	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10121	1	16	1	2	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	153	0	0	29	25	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	2	3	1	1	1	10120	2	16	2	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10120	1	16	1	2	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	27	1	1	1	10120	1	16	1	2	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	29	25	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	4	0	1	1	1	10120	2	16	2	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	4	0	1	1	1	10120	1	16	2	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20382	150	0	0	29	25	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20146	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10120	2	16	2	2	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	29	25	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	4	0	1	1	1	10121	2	16	1	2	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	4	0	1	1	1	10120	1	16	2	2	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20065	150	0	0	0	0	44	25	80010	10	80000	10	80000	50	640000	1	1	20030	20045	20049	3	21	80010	20	80000	20	160000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	7	0	0	0	10031	3	1	1	12	20	2	1	1	9	6	20042	15	160000	10	20046	20322	20054	20046	20046
160024	20045	150	0	0	0	0	44	25	80010	10	80000	10	80000	50	640000	1	1	20030	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	1	3	0	0	10027	3	1	1	8	20	2	1	1	4	8	20046	30	160000	10	20050	20290	20054	20046	20050
160024	20045	150	0	0	0	0	44	25	80010	10	80000	10	80000	50	640000	0	1	20026	20045	20045	3	21	80010	20	80000	20	160000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	1	0	0	0	10032	3	1	1	4	20	2	1	1	8	5	20042	15	160000	10	20046	20266	20066	20046	20378
160024	20045	150	0	0	0	0	44	25	80010	10	80000	10	80000	50	640000	1	1	20026	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10031	3	1	1	5	20	2	1	1	8	8	20042	15	160000	10	20046	20266	20066	20046	20046
160024	20045	150	0	0	0	0	44	25	80010	10	80000	10	80000	50	640000	0	1	20026	20049	20049	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10031	3	1	1	4	20	2	1	1	8	8	20042	15	160000	10	20046	20264	20066	20046	20046
160024	20045	150	0	0	0	0	44	25	80010	10	80000	10	80000	50	640000	1	1	20030	20045	20049	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10033	3	2	1	8	20	2	1	1	9	5	20042	15	160000	10	20046	20280	20054	20046	20046
160024	20045	150	0	0	0	0	44	25	80010	10	80000	10	80000	50	640000	1	1	20026	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	3	0	0	10027	6	1	1	6	24	2	1	2	4	8	20046	15	160000	10	20046	20247	20054	20046	20046
160024	20049	150	0	0	0	0	44	25	80010	10	80000	10	80000	50	640000	1	1	20026	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	18	0	0	10032	3	1	1	4	20	2	1	1	9	5	20042	30	160000	10	20050	20297	20054	20054	20046
160024	20049	150	0	0	0	0	44	25	80010	10	80000	10	80000	50	640000	1	1	20026	20045	20049	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10032	3	1	1	4	20	2	1	1	9	6	20042	15	160000	10	20046	20282	20054	20046	20046
160024	20045	150	0	0	0	0	44	25	80010	10	80000	10	80000	50	640000	0	1	20026	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10028	3	1	1	4	20	2	1	1	8	5	20042	15	160000	10	20046	20273	20054	20046	20046

Test 5: throughput

Count: 16

Code:

  ins v0.b[2], v16.b[1]
  ins v1.b[2], v16.b[1]
  ins v2.b[2], v16.b[1]
  ins v3.b[2], v16.b[1]
  ins v4.b[2], v16.b[1]
  ins v5.b[2], v16.b[1]
  ins v6.b[2], v16.b[1]
  ins v7.b[2], v16.b[1]
  ins v8.b[2], v16.b[1]
  ins v9.b[2], v16.b[1]
  ins v10.b[2], v16.b[1]
  ins v11.b[2], v16.b[1]
  ins v12.b[2], v16.b[1]
  ins v13.b[2], v16.b[1]
  ins v14.b[2], v16.b[1]
  ins v15.b[2], v16.b[1]

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	map dispatch bubble (d6)	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40100	300	0	0	0	12	0	0	71	0	25	160108	100	160008	100	160020	500	1280132	1	0	40477	40099	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	1	0	0	0	1	1	1	10118	5	1	16	0	40037	160000	100	40039	40058	40039	40039	40040
160204	40492	300	0	0	0	51	176	40	117	0	25	160108	100	160082	100	160020	500	1280132	0	5	40019	40099	40099	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	5	4	12	2	1	1	1	10118	5	1	16	0	40035	160000	100	40039	40091	40162	40058	40058
160204	40156	301	0	0	0	0	0	0	29	0	25	160108	100	160008	100	160020	500	1280132	1	5	40019	40038	40038	19977	23	19989	160121	200	160032	200	320064	40038	40039	1	1	160201	100	99	100	100	160000	100	0	24	0	0	0	1	1	1	10118	5	1	16	0	40096	160000	100	40039	40058	40277	40091	40102
160204	40057	299	0	0	0	0	0	0	29	0	25	160247	100	160147	100	160022	500	1280132	1	5	40137	40038	40057	20068	6	19989	160121	200	160032	200	320064	40038	40265	1	1	160201	100	99	100	100	160000	100	0	1	0	0	0	1	1	1	10118	5	1	16	0	40035	160000	100	40039	40058	40142	40039	40266
160204	40038	300	0	0	0	27	0	0	29	0	25	160109	100	160008	100	160020	500	1280132	1	5	40019	40038	40038	19977	6	19986	160120	200	160032	200	320064	40057	40038	1	1	160201	100	99	100	100	160000	100	0	1	0	1098	2	1	1	1	10118	5	1	16	0	40035	160000	100	40039	40040	40039	40039	40039
160204	40156	300	0	0	0	0	0	0	29	0	25	160182	100	160009	100	160020	500	1280132	0	5	40080	40099	40099	19977	6	20092	160120	200	160032	200	320064	40099	40099	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10118	5	1	16	0	40035	160000	100	40100	40074	40131	40040	40040
160204	40099	300	0	0	0	51	0	1	29	0	25	160108	100	160052	100	160021	500	1280132	0	5	40038	40038	40038	20012	6	20050	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	1	0	0	0	1	1	1	10118	5	1	16	0	40035	160000	100	40039	40040	40039	40039	40102
160204	40038	301	0	0	0	0	0	40	29	307	25	160247	100	160147	100	160022	500	1320130	0	5	40019	40038	40038	20012	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	1	0	0	0	1	1	1	10118	5	1	16	0	40035	160000	100	40039	40074	40131	40040	40058
160204	40039	300	0	0	0	0	0	1	712	110	25	160108	100	160023	100	160020	500	1280132	1	0	40080	40038	40099	19977	6	20050	160121	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10118	0	0	16	0	40035	160000	100	40039	40040	40039	40039	40139
160204	40087	300	0	0	0	0	0	0	29	125	25	160123	100	160008	100	160020	500	1280132	1	0	40019	40038	40038	20012	6	19989	160120	200	160032	200	320064	40038	40099	1	1	160201	100	99	100	100	160000	100	0	1	0	0	0	1	1	1	10118	0	0	16	0	40096	160000	100	40039	40058	40142	40102	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40074	300	0	0	0	0	24	711	0	25	160010	10	160000	10	160000	50	1280000	1	1	40019	0	40038	40112	20037	13	3	20059	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	30	0	0	10022	3	1	1	26	16	2	1	1	25	25	40035	20	8	160000	10	40039	40058	40040	40039	40058
160024	40038	301	0	0	0	0	275	46	0	25	160010	10	160000	10	160000	50	1280000	1	1	40019	0	40038	40057	19997	0	3	20018	160010	20	160726	20	320000	40038	40039	1	1	160021	10	9	10	10	160000	10	0	1	0	0	10022	3	1	1	11	16	2	1	2	25	13	40035	40	16	160000	10	40039	40048	40093	40039	40040
160024	40038	300	0	0	0	0	0	45	0	25	160011	10	160000	10	160000	50	1280000	1	1	40019	0	40038	40038	20138	7	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	4	5	0	0	10022	3	2	1	11	16	2	1	1	25	13	40035	20	8	160000	10	40039	40198	40088	40113	40113
160024	40112	299	0	0	0	0	19	69	0	25	160010	10	160019	10	160000	50	1280000	1	1	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40087	1	1	160021	10	9	10	10	160000	10	0	1	0	0	10022	3	1	1	12	16	2	1	1	25	11	40035	20	8	160000	10	40039	40057	40040	40039	40058
160024	40038	300	0	0	0	0	0	45	10	25	160010	10	160000	10	160000	50	1280000	1	1	40038	0	40038	40210	20138	7	3	20018	160010	20	160000	20	320000	40210	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	1	1	13	16	2	1	1	11	25	40207	20	8	160000	10	40039	40047	40040	40040	40039
160024	40038	301	0	0	0	0	0	45	0	44	160082	10	160046	10	160000	50	1320000	0	1	40191	0	40039	40038	19996	0	3	20037	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	6	1	1	11	16	2	1	2	25	13	40035	20	7	160000	10	40040	40091	40103	40039	40039
160024	40057	300	0	0	0	0	0	45	0	25	160010	10	160000	10	160000	50	3078935	1	1	40019	0	40057	40038	19996	7	3	20018	160010	20	160000	20	320000	40210	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	1	1	11	16	2	1	1	25	13	40035	20	8	160000	10	40039	40058	40040	40065	40039
160024	40038	300	0	0	0	0	275	67	0	25	160285	10	160000	10	160000	50	4037415	1	1	40019	0	40057	40210	20138	7	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	1	1	25	16	2	1	1	13	25	40035	20	8	160000	10	40039	40053	40079	40211	40039
160024	40038	299	0	0	0	0	0	46	0	25	160010	10	160000	10	160000	50	1280000	1	1	40217	0	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40072	1	1	160021	10	9	10	10	160000	10	0	1	0	0	10022	3	1	1	13	16	2	1	1	25	13	40035	20	8	160000	10	40039	40114	40039	40113	40039
160024	40039	300	0	1	0	0	0	45	0	25	160010	10	160000	10	160000	50	1280000	1	1	40093	0	40112	40038	19996	0	3	20092	160010	20	160000	20	320000	40112	40038	1	1	160021	10	9	10	10	160000	10	0	1	0	0	10022	3	1	1	25	16	2	1	1	25	25	40054	20	8	160000	10	40211	40047	40065	40064	40192

INS (element, B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations