Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

INS (element, D)

Test 1: uops

Code:

  ins v0.d[0], v1.d[1]
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715025116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715013216872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371536116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110002073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->1

Code:

  ins v0.d[0], v1.d[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371505161196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000030071021622197910100001002003820038200382003820038
10204200371502482196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038
10204200371500103196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000094071021622197913100001002003820038200382003820038
10204200371502161196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197915100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000200071021622197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038
10204200371500726196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03091e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500010319687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001019640216221978610000102003820038200382003820038
1002420037150006119687251001010100001010304502848963200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150106119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715002766119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500396119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001010640216221978510000102003820038200382003820038
1002420037150006119676251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 3: Latency 1->2

Code:

  ins v0.d[0], v0.d[1]
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715006119686251010010010000100100005002847521120018200372003718428618740101002001000820020016200372003711102011009910010010000100001117181619801100001002003820038200382003820038
10204200371501986119686251010010010000100100005002847521120018200372003718428718741101002001000820020016200372003711102011009910010010000100001117171619801100001002003820038200382003820038
1020420037150246119686251010010010000100100005002847521120018200372003718428718741101002001000820020016200372003711102011009910010010000100001117171619800100001002003820038200382003820038
102042003715006119686251010010010000100100005002847521120018200372003718428618741101002001000820020016200372003711102011009910010010000100001117171619800100001002003820038200382003820038
102042003715006119686251010010010000100100005002847521120018200372003718428718741101002001000820020016200372003711102011009910010010000100001117171619801100001002003820038200382003820038
102042003715006119686251010010010000100100005002847521120018200372003718428618740101002001000820020016200372003711102011009910010010000100001117181619800100001002003820038200382003820038
10204200371502466119686251010010010000100100005002847521120018200372003718428718740101002001000820020016200372003711102011009910010010000100001117181619800100001002003820038200382003820038
10204200371502676119686251010010010000100100005002847521120018200372003718428618741101002001000820020016200372003711102011009910010010000100001117181619801100001002003820038200382003820038
10204200371502466119686251010010010000100100005002847521120018200372003718428618741101002001000820020016200372003711102011009910010010000100001117171619801100001002003820038200382003820038
102042003715006119686251010010010000100100005002847521120018200372003718428718741101002001000820020016200372003711102011009910010010000100001117171619800100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500000006119686251001010100001010000502847521200182003720037184433187671001020100002020000200372003711100211091010100001000000006405165419786010000102003820038200382003820038
10024200371500000006119686251001010100001010000502847521200182003720037184433187671001020100002020000200372003711100211091010100001000000006405164519786010000102003820038200382003820038
10024200371500000255079619686251001010100001010000502847521200182003720037184433187671001020100002020000200372003711100211091010100001000000006405165519786010000102003820038200382003820038
10024200371500000006119686251001010100001010000502847521200182003720037184433187671001020100002020000200372003711100211091010100001000000006404165519786010000102003820038200382003820038
10024200371500000006119686251001010100001010000502847521200182003720037184433187671001020100002020000200372003711100211091010100001000000006405165519786010000102003820038200382003820038
1002420037150000028806119686251001010100001010000502847521200182003720037184433187671001020100002020000200372003711100211091010100001000000006404165419786010000102003820038200382003820038
10024200371500000006119686251001010100001010000502847521200182003720037184433187671001020100002020000200372003711100211091010100001000000006404164519786010000102003820038200382003820038
1002420037150000027006119686251001010100001010000502847521200182003720037184433187671001020100002020000200372003711100211091010100001000000006405164519786010000102003820038200382003820038
100242003715000009606119686251001010100001010000502847521200182003720037184433187671001020100002020000200372003711100211091010100001000000006404164519786010000102003820038200382003820038
10024200371500000006119686251001010100001010000502847521200182003720037184433187671001020100002020000200372003711100211091010100001000000006405165519786010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  ins v0.d[0], v8.d[1]
  movi v1.16b, 0
  ins v1.d[0], v8.d[1]
  movi v2.16b, 0
  ins v2.d[0], v8.d[1]
  movi v3.16b, 0
  ins v3.d[0], v8.d[1]
  movi v4.16b, 0
  ins v4.d[0], v8.d[1]
  movi v5.16b, 0
  ins v5.d[0], v8.d[1]
  movi v6.16b, 0
  ins v6.d[0], v8.d[1]
  movi v7.16b, 0
  ins v7.d[0], v8.d[1]
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602042009015000292580116100800161008002850064019602004420065200656128012820080028200160056200652006511160201100991001001600001000001111011901600200621600001002006620066201562006620066
160204200651501156292580116100800161008002850064019602004420065200656128012820080028200160056200652006511160201100991001001600001000001111011901600200621600001002006620066200662006620066
16020420065150002212580116100800161008002850064019612004420065200656128012820080028200160056200652006511160201100991001001600001000001111011901600200621600001002006620066200662006620066
1602042006515000292580116100800161008002850064019602004420065200656128012820080028200160056200652006511160201100991001001600001000031111011901600200621600001002006620066200662006620066
1602042006515000292580116100802171008002850064019612004420145200656128012820080028200160056200652006511160201100991001001600001002061111011901600200621600001002006620066200662006620066
16020420065150012292580116100800161008002850064019612004420065200656128012820080028200160056200652006511160201100991001001600001000031111011901600200621600001002006620066200662006620066
16020420065150012292580116100800161008002850064019602004420065200656128012820080028200160056200652006511160201100991001001600001000001111011901600200621600001002006620066200662006620066
1602042006515000292580116100800161008002850064019612004420065200656128012820080028200160056200652006511160201100991001001600001000001111011901600200621600001002006620066200662006620066
1602042006515000292580116100800161008002850064019612004420065200656128012820080028200160056200652006511160201100991001001600001000001111011901600200621600001002006620066200662006620066
1602042006515000292580116100800161008002850064019612004420065200656128012820080028200160056200652006511160201100991001001600001000001111011901600200621600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600242005815000050258001010800001080000506400000120026200512004532180010208000020160000200492004911160021109101016000010001003431210244221092004830160000102004620052200522004620050
16002420049150000502580010108000010800005064000001200302005120051321800102080000201600002004520051111600211091010160000100010034622102422210112004230160000102005020050200502004620046
16002420049150000442580010108000010800005064000001200302005120045321800102080000201600002005120051111600211091010160000100010036622112442211112004615160000102005020050200462005220050
16002420049150100502580010108000010800005064000001200302005120049321800102080000201600002004520049111600211091010160000100010037622112042210102004831160000102005020050200462005020046
16002420049150000502580010108000010800005064000011200302005120049321800102080000201600002004920049111600211091010160000100010034621102442212122004631160000102005020050200522005220052
16002420049150006502580010108000010800005064000001200302004920049321800102080000201600002004520049111600211091010160000100010036621122422211122004630160000102005020050200502005020050
16002420051150000502580010108000010800005064000001200302004920049321800102080000201600002004520049111600211091010160000100010037322122442211112004630160000102005020050200502005020050
16002420049150000502580010108000010800005064000001200302004920049321800102080000201600002005120045111600211091010160000100010037622112442211112004631160000102004620050200502005220050
16002420049150000502580010108000010800005064000011200302004920049321800102080000201600002004920049111600211091010160000100010036621112622210112004815160000102005020052200502005020050
16002420049150000442580010108000010800005064000001200302004920049321800102080000201600002004520049111600211091010160000100010037622112442212122004630160000102005220050200502005020052

Test 5: throughput

Count: 16

Code:

  ins v0.d[0], v16.d[1]
  ins v1.d[0], v16.d[1]
  ins v2.d[0], v16.d[1]
  ins v3.d[0], v16.d[1]
  ins v4.d[0], v16.d[1]
  ins v5.d[0], v16.d[1]
  ins v6.d[0], v16.d[1]
  ins v7.d[0], v16.d[1]
  ins v8.d[0], v16.d[1]
  ins v9.d[0], v16.d[1]
  ins v10.d[0], v16.d[1]
  ins v11.d[0], v16.d[1]
  ins v12.d[0], v16.d[1]
  ins v13.d[0], v16.d[1]
  ins v14.d[0], v16.d[1]
  ins v15.d[0], v16.d[1]
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)daddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602044008929907810747125160158100160008100160021500128013200400194003840038199980619989160120200160032200320064400954003811160201100991001001600001000011110118016000400351600001004018340039401834003940183
1602044018230000297125160268100160008100160021500551955000400194003840038200070620046160120200160032200320064400954003811160201100991001001600001000011110118016000401381600001004003940096400964014240039
160204400383000782911125160178100160008100160020500556568800400204003840057200680620008160120200160032200320064400574003911160201100991001001600001000011110118016000400351600001004003940040400564003940086
160204400743000056025160108100160078100160020500551832000400194009540038200070619989160120200160032200320064402004005711160201100991001001600001000011110118016000400921600001004003940096400964003940096
16020440038300078297125160158100160058100160020500128013200400194007440038199870619989160120200160032200320064400954014111160201100991001001600001000011110118016000400771600001004010040039400964009640039
16020440141300005611125160228100160008100160020500128013200400194009540038200070620046160120200160032200320064400954009511160201100991001001600001000011110118016000400921600001004003940096400964003940096
1602044003830000293425160108100160008100160020500556568800400764003840095199770619989160120200160032200320064400384009511160201100991001001600001000011110118016000401791600001004018340039401834003940183
1602044003830001810261601171001600171001600285001280196014002840048400852004627920023160128200160038200320076400854004911160201100991001001600001001322210128123011400451600001004005040081401454004940096
1602044004830001935027160158100160017100160028500136513400400804018240048199760920023160120200160038200320076400494008011160201100991001001600001000022210129123012400461600001004014540050400814014540107
16020440085300012980111271601741001601151001600285001316997004002940048400841997624920023160128200160038200320060401444004811160201100991001001600001000022210129123011400461600001004004940086401354014540230

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f373a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acc2branch mispred nonspec (cb)cdcfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600244023030000000000106045025160010101600231016000050131999811540071040064400391999603200191600102016000020320000400384006011160021109101016000010000300010024115231162111913401091510160000104003940085400394008540039
1600244003929900000000004570251600701016006010160000504728951115400930400384009020015032006416001020160000203200004008440038111600211091010160000100007500010024115211164221220400843010160000104011340039400394009140039
160024400383000000000045067025160010101600001016000050491801911540019040038401121999620320064160010201600002032000040038401121116002110910101600001000030000100228411316211121940035155160000104003940076400394007640039
16002440039299000000000066025160011101600001016000050472895111540019040039400581999603200181600102016000020320000400384008411160021109101016000010001087000100228411116211141140035155160000104008540039400404003940039
160024400383000000000060073025160011101600001016000050472895111540071040084400381999603200181600102016000020320000401124003811160021109101016000010000000010024115211164221113400813010160000104003940085400394008540039
16002440075300000001006006702516001010160024101600005012800000154009304011240038199960320018160010201600002032000040112400381116002110910101600001000021000100228411316211131440036155160000104003940040400394003940039
1600244003829900000000006970251600701016006010160000501320000115400650400844003819996032001816001020160000203200004003840084111600211091010160000100002100010024115212164221113400353010160000104004040039400394004040039
1600244003830000000000005102516001010160000101600005012800001154001904003840038200370320070160010201600002032000040084400381116002110910101600001000060001002211511416211141140036155160000104008540039400404003940040
1600244006429900000000004570251600701016006010160000504728951115400190400394008420015032006416001020160000203200004008440038111600211091010160000100000000100228411216211141140055155160000104003940039400614005840040
16002440039299000000000023502516007010160060101600005012800001154001904003840038199960320018160010201600002032000040084400381116002110910101600001000024000100228411316211131340035155160000104008540039400394004040102