Firestorm: INS (element, D) measurements

Code:

  ins v0.d[0], v1.d[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	0	251	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	132	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	3	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	2	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  ins v0.d[0], v1.d[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	51	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	3	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	24	82	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	103	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	9	4	0	710	2	16	2	2	19791	3	10000	100	20038	20038	20038	20038	20038
10204	20037	150	21	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	19791	5	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	2	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	726	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	103	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	1	9	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10304	50	2848963	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	1	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	276	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	39	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	1	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19676	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  ins v0.d[0], v0.d[1]

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	16	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	198	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	16	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	24	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	16	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	16	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	16	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	16	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	246	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	7	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	16	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	267	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	16	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	246	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	16	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	16	19800	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	5	16	5	4	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	5	16	4	5	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	255	0	796	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	5	16	5	5	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	4	16	5	5	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	5	16	5	5	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	288	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	4	16	5	4	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	4	16	4	5	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	270	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	5	16	4	5	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	96	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	4	16	4	5	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	5	16	5	5	19786	0	10000	10	20038	20038	20038	20038	20038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  ins v0.d[0], v8.d[1]
  movi v1.16b, 0
  ins v1.d[0], v8.d[1]
  movi v2.16b, 0
  ins v2.d[0], v8.d[1]
  movi v3.16b, 0
  ins v3.d[0], v8.d[1]
  movi v4.16b, 0
  ins v4.d[0], v8.d[1]
  movi v5.16b, 0
  ins v5.d[0], v8.d[1]
  movi v6.16b, 0
  ins v6.d[0], v8.d[1]
  movi v7.16b, 0
  ins v7.d[0], v8.d[1]

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20090	150	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20156	20066	20066
160204	20065	150	1	156	29	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	221	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	3	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80217	100	80028	500	640196	1	20044	20145	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	2	0	6	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	12	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	3	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	12	29	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20058	150	0	0	0	50	25	80010	10	80000	10	80000	50	640000	0	1	20026	20051	20045	3	21	80010	20	80000	20	160000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	10034	3	1	2	10	24	4	2	2	10	9	20048	30	160000	10	20046	20052	20052	20046	20050
160024	20049	150	0	0	0	50	25	80010	10	80000	10	80000	50	640000	0	1	20030	20051	20051	3	21	80010	20	80000	20	160000	20045	20051	1	1	160021	10	9	10	10	160000	10	0	0	10034	6	2	2	10	24	2	2	2	10	11	20042	30	160000	10	20050	20050	20050	20046	20046
160024	20049	150	0	0	0	44	25	80010	10	80000	10	80000	50	640000	0	1	20030	20051	20045	3	21	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	10036	6	2	2	11	24	4	2	2	11	11	20046	15	160000	10	20050	20050	20046	20052	20050
160024	20049	150	1	0	0	50	25	80010	10	80000	10	80000	50	640000	0	1	20030	20051	20049	3	21	80010	20	80000	20	160000	20045	20049	1	1	160021	10	9	10	10	160000	10	0	0	10037	6	2	2	11	20	4	2	2	10	10	20048	31	160000	10	20050	20050	20046	20050	20046
160024	20049	150	0	0	0	50	25	80010	10	80000	10	80000	50	640000	1	1	20030	20051	20049	3	21	80010	20	80000	20	160000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	10034	6	2	1	10	24	4	2	2	12	12	20046	31	160000	10	20050	20050	20052	20052	20052
160024	20049	150	0	0	6	50	25	80010	10	80000	10	80000	50	640000	0	1	20030	20049	20049	3	21	80010	20	80000	20	160000	20045	20049	1	1	160021	10	9	10	10	160000	10	0	0	10036	6	2	1	12	24	2	2	2	11	12	20046	30	160000	10	20050	20050	20050	20050	20050
160024	20051	150	0	0	0	50	25	80010	10	80000	10	80000	50	640000	0	1	20030	20049	20049	3	21	80010	20	80000	20	160000	20045	20049	1	1	160021	10	9	10	10	160000	10	0	0	10037	3	2	2	12	24	4	2	2	11	11	20046	30	160000	10	20050	20050	20050	20050	20050
160024	20049	150	0	0	0	50	25	80010	10	80000	10	80000	50	640000	0	1	20030	20049	20049	3	21	80010	20	80000	20	160000	20051	20045	1	1	160021	10	9	10	10	160000	10	0	0	10037	6	2	2	11	24	4	2	2	11	11	20046	31	160000	10	20046	20050	20050	20052	20050
160024	20049	150	0	0	0	50	25	80010	10	80000	10	80000	50	640000	1	1	20030	20049	20049	3	21	80010	20	80000	20	160000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	10036	6	2	1	11	26	2	2	2	10	11	20048	15	160000	10	20050	20052	20050	20050	20050
160024	20049	150	0	0	0	44	25	80010	10	80000	10	80000	50	640000	0	1	20030	20049	20049	3	21	80010	20	80000	20	160000	20045	20049	1	1	160021	10	9	10	10	160000	10	0	0	10037	6	2	2	11	24	4	2	2	12	12	20046	30	160000	10	20052	20050	20050	20050	20052

Test 5: throughput

Count: 16

Code:

  ins v0.d[0], v16.d[1]
  ins v1.d[0], v16.d[1]
  ins v2.d[0], v16.d[1]
  ins v3.d[0], v16.d[1]
  ins v4.d[0], v16.d[1]
  ins v5.d[0], v16.d[1]
  ins v6.d[0], v16.d[1]
  ins v7.d[0], v16.d[1]
  ins v8.d[0], v16.d[1]
  ins v9.d[0], v16.d[1]
  ins v10.d[0], v16.d[1]
  ins v11.d[0], v16.d[1]
  ins v12.d[0], v16.d[1]
  ins v13.d[0], v16.d[1]
  ins v14.d[0], v16.d[1]
  ins v15.d[0], v16.d[1]

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40089	299	0	78	1074	71	25	160158	100	160008	100	160021	500	1280132	0	0	40019	40038	40038	19998	0	6	19989	160120	200	160032	200	320064	40095	40038	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	0	40035	160000	100	40183	40039	40183	40039	40183
160204	40182	300	0	0	29	71	25	160268	100	160008	100	160021	500	5519550	0	0	40019	40038	40038	20007	0	6	20046	160120	200	160032	200	320064	40095	40038	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	0	40138	160000	100	40039	40096	40096	40142	40039
160204	40038	300	0	78	29	111	25	160178	100	160008	100	160020	500	5565688	0	0	40020	40038	40057	20068	0	6	20008	160120	200	160032	200	320064	40057	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	0	40035	160000	100	40039	40040	40056	40039	40086
160204	40074	300	0	0	56	0	25	160108	100	160078	100	160020	500	5518320	0	0	40019	40095	40038	20007	0	6	19989	160120	200	160032	200	320064	40200	40057	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	0	40092	160000	100	40039	40096	40096	40039	40096
160204	40038	300	0	78	29	71	25	160158	100	160058	100	160020	500	1280132	0	0	40019	40074	40038	19987	0	6	19989	160120	200	160032	200	320064	40095	40141	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	0	40077	160000	100	40100	40039	40096	40096	40039
160204	40141	300	0	0	56	111	25	160228	100	160008	100	160020	500	1280132	0	0	40019	40095	40038	20007	0	6	20046	160120	200	160032	200	320064	40095	40095	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	0	40092	160000	100	40039	40096	40096	40039	40096
160204	40038	300	0	0	29	34	25	160108	100	160008	100	160020	500	5565688	0	0	40076	40038	40095	19977	0	6	19989	160120	200	160032	200	320064	40038	40095	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	0	40179	160000	100	40183	40039	40183	40039	40183
160204	40038	300	0	1	81	0	26	160117	100	160017	100	160028	500	1280196	0	1	40028	40048	40085	20046	27	9	20023	160128	200	160038	200	320076	40085	40049	1	1	160201	100	99	100	100	160000	100	1	3	2	2	2	10128	1	23	0	1	1	40045	160000	100	40050	40081	40145	40049	40096
160204	40048	300	0	1	935	0	27	160158	100	160017	100	160028	500	1365134	0	0	40080	40182	40048	19976	0	9	20023	160120	200	160038	200	320076	40049	40080	1	1	160201	100	99	100	100	160000	100	0	0	2	2	2	10129	1	23	0	1	2	40046	160000	100	40145	40050	40081	40145	40107
160204	40085	300	0	129	80	111	27	160174	100	160115	100	160028	500	1316997	0	0	40029	40048	40084	19976	24	9	20023	160128	200	160038	200	320060	40144	40048	1	1	160201	100	99	100	100	160000	100	0	0	2	2	2	10129	1	23	0	1	1	40046	160000	100	40049	40086	40135	40145	40230

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40230	300	0	0	0	0	0	0	0	0	106	0	45	0	25	160010	10	160023	10	160000	50	1319998	1	1	5	40071	0	40064	40039	19996	0	3	20019	160010	20	160000	20	320000	40038	40060	1	1	160021	10	9	10	10	160000	10	0	0	0	3	0	0	0	10024	11	5	2	31	16	2	1	1	19	13	40109	15	10	160000	10	40039	40085	40039	40085	40039
160024	40039	299	0	0	0	0	0	0	0	0	0	0	45	70	25	160070	10	160060	10	160000	50	4728951	1	1	5	40093	0	40038	40090	20015	0	3	20064	160010	20	160000	20	320000	40084	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	75	0	0	0	10024	11	5	2	11	16	4	2	2	12	20	40084	30	10	160000	10	40113	40039	40039	40091	40039
160024	40038	300	0	0	0	0	0	0	0	0	45	0	67	0	25	160010	10	160000	10	160000	50	4918019	1	1	5	40019	0	40038	40112	19996	20	3	20064	160010	20	160000	20	320000	40038	40112	1	1	160021	10	9	10	10	160000	10	0	0	0	30	0	0	0	10022	8	4	1	13	16	2	1	1	12	19	40035	15	5	160000	10	40039	40076	40039	40076	40039
160024	40039	299	0	0	0	0	0	0	0	0	0	0	66	0	25	160011	10	160000	10	160000	50	4728951	1	1	5	40019	0	40039	40058	19996	0	3	20018	160010	20	160000	20	320000	40038	40084	1	1	160021	10	9	10	10	160000	10	0	0	10	87	0	0	0	10022	8	4	1	11	16	2	1	1	14	11	40035	15	5	160000	10	40085	40039	40040	40039	40039
160024	40038	300	0	0	0	0	0	0	0	0	60	0	73	0	25	160011	10	160000	10	160000	50	4728951	1	1	5	40071	0	40084	40038	19996	0	3	20018	160010	20	160000	20	320000	40112	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10024	11	5	2	11	16	4	2	2	11	13	40081	30	10	160000	10	40039	40085	40039	40085	40039
160024	40075	300	0	0	0	0	0	1	0	0	60	0	67	0	25	160010	10	160024	10	160000	50	1280000	0	1	5	40093	0	40112	40038	19996	0	3	20018	160010	20	160000	20	320000	40112	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	21	0	0	0	10022	8	4	1	13	16	2	1	1	13	14	40036	15	5	160000	10	40039	40040	40039	40039	40039
160024	40038	299	0	0	0	0	0	0	0	0	0	0	69	70	25	160070	10	160060	10	160000	50	1320000	1	1	5	40065	0	40084	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40084	1	1	160021	10	9	10	10	160000	10	0	0	0	21	0	0	0	10024	11	5	2	12	16	4	2	2	11	13	40035	30	10	160000	10	40040	40039	40039	40040	40039
160024	40038	300	0	0	0	0	0	0	0	0	0	0	51	0	25	160010	10	160000	10	160000	50	1280000	1	1	5	40019	0	40038	40038	20037	0	3	20070	160010	20	160000	20	320000	40084	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	6	0	0	0	10022	11	5	1	14	16	2	1	1	14	11	40036	15	5	160000	10	40085	40039	40040	40039	40040
160024	40064	299	0	0	0	0	0	0	0	0	0	0	45	70	25	160070	10	160060	10	160000	50	4728951	1	1	5	40019	0	40039	40084	20015	0	3	20064	160010	20	160000	20	320000	40084	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	8	4	1	12	16	2	1	1	14	11	40055	15	5	160000	10	40039	40039	40061	40058	40040
160024	40039	299	0	0	0	0	0	0	0	0	0	0	235	0	25	160070	10	160060	10	160000	50	1280000	1	1	5	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40084	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	24	0	0	0	10022	8	4	1	13	16	2	1	1	13	13	40035	15	5	160000	10	40085	40039	40039	40040	40102

INS (element, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations