Firestorm: INS (element, H) measurements

Code:

  ins v0.h[2], v1.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	2	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	251	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	6	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	84	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	105	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	103	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  ins v0.h[2], v1.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	726	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	82	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	1	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19824	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	66	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	3	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	1	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	126	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	145	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20084	2	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	166	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20133	20086	20038
10024	20037	150	1	0	88	193	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	103	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	145	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	145	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	103	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  ins v0.h[2], v0.h[1]

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	103	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	0	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	0	0	1	1	1	717	0	16	0	0	19800	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	12	0	557	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18409	0	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	5	0	0	1	1	1	722	2	24	2	2	19787	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	97	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18409	0	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	722	2	24	2	2	19787	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	202	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18409	0	6	18733	10256	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	717	0	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	0	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	5	0	0	1	1	1	718	0	16	0	0	19800	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	0	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	718	0	16	0	0	19800	0	10000	100	20038	20038	20087	20038	20038
10204	20037	150	0	0	0	82	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	0	7	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	0	0	1	1	1	718	0	16	0	0	19864	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	0	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	717	0	16	0	0	19800	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	0	6	18759	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	718	0	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	0	7	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	5	0	0	1	1	1	717	0	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	89	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20086
10024	20083	150	0	235	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	1	0	0	0	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	324	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	1	0	0	0	0	0	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	3	16	3	3	19786	10000	10	20180	20038	20038	20038	20038
10024	20037	149	0	362	19686	25	10010	10	10000	10	10000	50	2848235	1	20018	20037	20037	18443	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  ins v0.h[2], v8.h[1]
  movi v1.16b, 0
  ins v1.h[2], v8.h[1]
  movi v2.16b, 0
  ins v2.h[2], v8.h[1]
  movi v3.16b, 0
  ins v3.h[2], v8.h[1]
  movi v4.16b, 0
  ins v4.h[2], v8.h[1]
  movi v5.16b, 0
  ins v5.h[2], v8.h[1]
  movi v6.16b, 0
  ins v6.h[2], v8.h[1]
  movi v7.16b, 0
  ins v7.h[2], v8.h[1]

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20077	151	0	0	113	25	80116	100	80016	100	80028	500	640196	0	20044	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10119	4	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	138	25	80116	100	80016	100	80028	500	640196	0	20044	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10119	0	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10119	0	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10119	0	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10119	0	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10119	0	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10119	0	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10119	0	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	92	25	80116	100	80016	100	80028	500	640196	0	20044	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10119	0	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10119	0	16	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20069	151	0	0	0	0	0	0	0	44	25	80010	10	80000	10	80000	50	640000	1	1	20026	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10026	3	1	1	4	24	2	1	12	3	3	20042	15	160000	10	20046	20046	20046	20046	20046
160024	20045	151	0	0	0	0	0	0	0	44	25	80010	10	80000	10	80000	50	640000	1	1	20089	20132	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10027	3	1	1	4	20	2	1	12	3	4	20042	15	160000	10	20046	20046	20050	20046	20046
160024	20045	150	0	0	0	0	0	0	0	44	25	80010	10	80000	10	80000	50	640000	1	1	20026	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10027	3	1	1	5	20	4	1	11	4	4	20042	15	160000	10	20046	20046	20046	20046	20046
160024	20045	150	0	0	0	0	0	0	0	370	25	80010	10	80000	10	80000	50	640000	1	1	20026	20045	20045	3	21	80010	20	80129	20	160000	20045	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10027	3	1	1	4	20	2	1	10	5	4	20042	15	160000	10	20046	20046	20046	20046	20046
160024	20045	150	0	0	0	0	0	0	0	44	25	80010	10	80000	10	80000	50	640000	1	1	20026	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10028	3	1	1	5	20	2	1	10	4	5	20042	15	160000	10	20046	20046	20046	20046	20046
160024	20045	150	0	0	0	0	0	0	0	44	25	80010	10	80000	10	80000	50	640000	1	1	20030	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10025	3	1	1	5	24	2	1	13	3	2	20042	15	160000	10	20050	20050	20046	20046	20046
160024	20045	150	0	0	1	0	0	0	0	151	25	80010	10	80000	10	80000	50	640000	1	1	20026	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	3	0	10026	6	1	2	4	24	4	2	16	4	4	20050	30	160000	10	20046	20046	20046	20046	20046
160024	20045	150	0	0	0	0	0	0	0	614	25	80010	10	80000	10	80000	50	640000	1	1	20026	20045	20045	3	21	80010	20	80000	20	160000	20045	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10028	3	1	1	2	20	2	1	10	4	4	20042	15	160000	10	20046	20046	20046	20046	20113
160024	20045	150	0	0	0	0	0	0	0	157	25	80010	10	80000	10	80000	50	640000	0	1	20026	20045	20049	3	21	80010	20	80000	20	160000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10027	3	2	1	4	20	2	2	13	4	3	20042	15	160000	10	20046	20046	20046	20046	20046
160024	20045	150	0	0	0	0	0	0	0	44	25	80010	10	80000	10	80000	50	640000	1	1	20026	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10027	3	1	1	4	20	2	1	11	4	3	20042	15	160000	10	20046	20046	20046	20046	20050

Test 5: throughput

Count: 16

Code:

  ins v0.h[2], v16.h[1]
  ins v1.h[2], v16.h[1]
  ins v2.h[2], v16.h[1]
  ins v3.h[2], v16.h[1]
  ins v4.h[2], v16.h[1]
  ins v5.h[2], v16.h[1]
  ins v6.h[2], v16.h[1]
  ins v7.h[2], v16.h[1]
  ins v8.h[2], v16.h[1]
  ins v9.h[2], v16.h[1]
  ins v10.h[2], v16.h[1]
  ins v11.h[2], v16.h[1]
  ins v12.h[2], v16.h[1]
  ins v13.h[2], v16.h[1]
  ins v14.h[2], v16.h[1]
  ins v15.h[2], v16.h[1]

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40060	300	0	0	0	530	0	25	160233	100	160008	100	160020	500	1280132	0	0	5	40019	40038	40038	20030	14	6	20016	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	5	0	0	0	16	0	2	1	0	0	40035	0	0	160000	100	40039	40113	40039	40113	40039
160204	40112	300	0	0	0	52	0	25	160108	100	160008	100	160020	500	3079067	0	1	5	40019	40038	40038	19977	14	6	19989	160120	200	160032	200	320064	40039	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	5	0	0	0	16	0	0	1	0	0	40035	0	0	160000	100	40058	40133	40039	40039	40039
160204	40038	301	0	0	19	29	0	25	160108	100	160008	100	160020	500	1280132	0	0	5	40019	40132	40038	19977	0	6	19989	160121	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	0	0	0	0	16	0	0	0	0	0	40035	0	0	160000	100	40133	40039	40133	40039	40039
160204	40132	300	0	0	31	51	168	25	160183	100	160008	100	160020	500	1280132	0	0	5	40113	40038	40057	19977	0	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	5	0	0	0	16	0	0	0	0	0	40035	0	0	160000	100	40113	40039	40039	40039	40039
160204	40038	299	0	0	19	47	3	25	160108	100	160133	100	160020	500	1280132	0	1	0	40038	40057	40038	19977	0	6	20009	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	0	0	0	0	16	0	0	0	0	0	40035	0	0	160000	100	40039	40039	40064	40039	40039
160204	40038	299	0	0	0	39	0	25	160199	100	160008	100	160020	500	1280132	0	0	5	40019	40038	40132	19977	0	6	20057	160120	200	160032	200	320064	40038	40064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	5	0	0	0	16	0	0	0	0	0	40035	0	0	160000	100	40059	40039	40039	40039	40058
160204	40038	300	0	0	73	29	0	25	160108	100	160017	100	160020	500	1280132	0	1	5	40019	40038	40039	19977	0	6	20008	160120	200	160032	200	320064	40220	40064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	5	0	0	0	16	0	0	1	0	0	40036	0	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	29	0	25	160108	100	160008	100	160020	500	3079067	0	0	5	40019	40038	40132	20039	0	6	19989	160120	200	160032	200	320064	40039	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	5	0	0	0	16	0	0	0	0	0	40035	0	0	160000	100	40058	40039	40058	40039	40113
160204	40038	299	0	0	133	29	0	25	160108	100	160239	100	160020	500	1280132	0	1	0	40038	40038	40038	19977	0	6	20008	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	0	0	0	0	16	0	0	0	0	0	40054	0	0	160000	100	40039	40056	40039	40039	40113
160204	40112	300	0	0	32	220	0	25	160108	100	160008	100	160020	500	1280132	0	1	0	40019	40038	40038	19977	0	6	19989	160120	200	160032	200	320064	40038	40087	1	1	160201	100	99	100	100	160000	100	0	0	0	15	1	1	1	10118	5	0	0	0	48	0	0	0	0	0	40035	0	0	160000	100	40039	40039	40039	40332	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	st unit uop (a7)	l1d cache writeback (a8)	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40078	300	0	86	0	45	70	25	160070	10	160060	10	160000	50	1280000	1	1	5	40019	40038	40084	20015	0	3	20104	160010	20	160000	20	320000	40126	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	2	1	21	16	2	1	1	18	21	40081	21	8	160000	10	40039	40085	40039	40085	40039
160024	40038	300	0	0	0	67	0	25	160010	10	160000	10	160000	50	5516100	1	1	5	40020	40084	40038	19996	0	3	20018	160010	20	160000	20	320000	40090	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	2	1	24	17	4	2	2	22	19	40035	20	8	160000	10	40039	40040	40088	40065	40059
160024	40038	300	0	60	0	67	0	25	160010	10	160000	10	160000	50	1319998	1	1	5	40019	40038	40039	19996	0	3	20018	160010	20	160000	20	320000	40055	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	10024	8	2	1	24	16	2	1	1	18	18	40109	20	8	160000	10	40039	40085	40039	40085	40039
160024	40038	300	3	0	0	45	70	25	160070	10	160060	10	160000	50	3078935	1	1	5	40045	40084	40038	19997	0	3	20067	160010	20	160000	20	320000	40095	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	2	1	18	16	1	2	1	20	18	40081	20	8	160000	10	40040	40039	40113	40039	40039
160024	40038	300	0	106	0	67	149	25	160010	10	160068	10	160000	50	1280000	1	1	5	40019	40075	40038	19996	0	3	20045	160118	20	160000	20	320000	40043	40038	1	1	160021	10	9	10	10	160000	10	0	0	1	10022	8	2	1	17	16	2	1	1	18	20	40035	20	16	160000	10	40039	40076	40058	40088	40085
160024	40087	300	0	0	0	67	39	25	160011	10	160023	10	160000	50	1280000	1	1	5	40019	40038	40143	19996	0	3	20018	160010	20	160000	20	320000	40090	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	2	1	14	16	2	1	1	17	15	40035	21	8	160000	10	40113	40039	40039	40039	40039
160024	40038	300	0	45	0	67	39	25	160055	10	160045	10	160000	50	1280000	1	1	5	40019	40058	40084	20015	0	3	20064	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	3	1	16	16	2	2	2	18	15	40054	41	8	160000	10	40039	40113	40039	40144	40040
160024	40039	300	0	0	14	67	70	25	160070	10	160060	10	160000	50	1280000	0	1	5	40019	40038	40084	20015	0	3	20064	160010	20	160000	20	320000	40041	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	3	1	18	16	1	1	1	18	21	40109	20	16	160000	10	40039	40076	40039	40113	40113
160024	40038	300	0	0	0	235	70	50	160078	10	160001	10	160000	50	1280000	1	1	5	40019	40038	40084	19996	0	3	20064	160010	20	160000	20	320000	40059	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	2	1	16	16	2	1	2	20	22	40081	20	7	160000	10	40040	40039	40113	40039	40113
160024	40112	300	0	60	0	67	0	25	160010	10	160000	10	160000	50	5516100	0	1	5	40065	40038	40112	19996	0	3	20018	160010	20	160000	20	320000	40072	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	3	2	20	16	1	2	2	19	19	40035	21	8	160000	10	40039	40113	40039	40113	40039

INS (element, H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations