Firestorm: INS (element, S) measurements

Code:

  ins v0.s[2], v1.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	16	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	41	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	9	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  ins v0.s[2], v1.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	441	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19687	25	10116	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18764	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	483	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	670	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	251	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	103	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	690	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	709	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	124	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	1	0	650	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	44	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	82	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	149	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  ins v0.s[2], v0.s[1]

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	279	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	2115	1	1	1	717	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	718	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	717	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	519	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	718	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	462	1	97	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	722	2	24	2	2	19787	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	1	97	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	1	0	0	1	1	1	722	2	24	2	2	19787	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	1	97	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	722	2	24	2	2	19787	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	378	1	97	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	722	2	24	2	2	19787	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	1	97	19686	25	10116	100	10000	100	10000	500	2847521	1	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	722	2	24	2	2	19787	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	1	97	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	722	2	24	2	2	19787	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20320	150	1	7	7	1170	704	4377	19596	181	10108	14	10096	14	11216	94	2860391	0	20306	20371	20417	18475	0	37	18942	11231	22	11338	24	22674	20417	20511	10	1	10021	10	9	10	10	10000	10	2	2	0	17713	827	5	81	3	2	20074	1	10000	10	20415	20417	20466	20455	20371
10024	20513	152	0	11	10	240	264	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	7	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	27	0	61	19686	25	10010	10	10000	10	10152	50	2847521	0	20018	20037	20037	18443	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	30	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20083
10024	20037	150	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  ins v0.s[2], v8.s[1]
  movi v1.16b, 0
  ins v1.s[2], v8.s[1]
  movi v2.16b, 0
  ins v2.s[2], v8.s[1]
  movi v3.16b, 0
  ins v3.s[2], v8.s[1]
  movi v4.16b, 0
  ins v4.s[2], v8.s[1]
  movi v5.16b, 0
  ins v5.s[2], v8.s[1]
  movi v6.16b, 0
  ins v6.s[2], v8.s[1]
  movi v7.16b, 0
  ins v7.s[2], v8.s[1]

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20089	150	132	29	25	80116	100	80016	100	80028	500	640196	0	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	0	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066
160205	20065	150	78	29	25	80116	100	80016	100	80028	500	640196	0	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	537	29	25	80116	100	80016	100	80028	500	640196	0	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	608	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	29	25	80116	100	80016	100	80028	500	640196	0	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	0	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	672	29	25	80116	100	80016	100	80028	500	640196	0	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	0	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	69	25	80116	100	80016	100	80028	500	640196	0	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	0	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20091	150	30	0	109	27	80010	10	80000	10	80000	50	640000	1	1	5	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	1	0	3	0	10034	8	4	1	18	25	2	1	1	12	7	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	21	0	44	27	80010	10	80000	10	80000	50	640000	1	1	5	20271	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10034	8	3	1	7	25	2	1	1	10	11	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	252	0	44	27	80010	10	80000	10	80000	50	640000	1	1	5	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10029	8	3	1	11	25	2	1	1	6	11	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	423	0	44	27	80010	10	80000	10	80000	50	640000	1	1	5	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10030	8	3	1	11	25	2	1	1	11	11	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	44	27	80010	10	80000	10	80000	50	640000	1	1	5	20031	20050	20050	3	21	80010	20	80000	20	160000	20130	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	1	4	0	0	10034	8	3	1	13	25	2	1	1	11	6	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	360	0	44	27	80010	10	80000	10	80000	50	640000	1	1	5	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10034	8	3	1	8	25	2	1	1	12	12	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20057	150	330	0	44	27	80010	10	80000	10	80000	50	640000	1	1	5	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10030	8	3	1	11	25	2	1	1	6	11	20047	20	1	160000	10	20051	20051	20051	20060	20051
160024	20050	150	18	0	44	27	80010	10	80000	10	80000	50	640000	1	1	5	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	3	0	10035	8	3	1	12	25	2	1	1	12	7	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	9	0	44	27	80010	10	80000	10	80000	50	640000	1	1	5	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10034	8	3	1	6	25	2	1	1	11	6	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	176	44	27	80010	10	80000	10	80000	50	640000	1	1	5	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	2	0	0	0	0	0	10030	8	3	1	11	25	2	1	1	7	12	20047	20	1	160000	10	20051	20051	20051	20051	20051

Test 5: throughput

Count: 16

Code:

  ins v0.s[2], v16.s[1]
  ins v1.s[2], v16.s[1]
  ins v2.s[2], v16.s[1]
  ins v3.s[2], v16.s[1]
  ins v4.s[2], v16.s[1]
  ins v5.s[2], v16.s[1]
  ins v6.s[2], v16.s[1]
  ins v7.s[2], v16.s[1]
  ins v8.s[2], v16.s[1]
  ins v9.s[2], v16.s[1]
  ins v10.s[2], v16.s[1]
  ins v11.s[2], v16.s[1]
  ins v12.s[2], v16.s[1]
  ins v13.s[2], v16.s[1]
  ins v14.s[2], v16.s[1]
  ins v15.s[2], v16.s[1]

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2504

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40095	300	0	0	0	0	30	0	25	160206	100	160008	100	160022	500	1320132	40054	40073	40039	19977	6	20049	160122	200	160032	200	320064	40075	40038	1	1	160201	100	99	100	100	160000	100	4	3	1	1	1	10118	0	16	0	0	40081	160000	100	40040	40088	40065	40040	40040
160204	40084	300	0	0	0	39	29	149	25	160123	100	160008	100	160020	500	5438490	40020	40039	40039	19977	6	20015	160122	200	160032	200	320064	40039	40038	1	1	160201	100	99	100	100	160000	100	0	3	1	1	1	10118	0	16	0	0	40070	160000	100	40074	40040	40040	40040	40039
160204	40065	300	0	0	0	0	531	28	25	160123	100	160017	100	160022	500	5516250	40054	40073	40039	19977	6	20013	160122	200	160032	200	320064	40038	40084	1	1	160201	100	99	100	100	160000	100	0	3	1	1	1	10118	0	16	0	0	40070	160000	100	40074	40040	40074	40040	40083
160204	40039	300	0	0	0	45	29	28	25	160198	100	160008	100	160021	500	1320132	40020	40039	40039	19997	6	20035	160122	200	160032	200	320064	40039	40073	1	1	160201	100	99	100	100	160000	100	1	12	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40039	40085	40040	40085
160204	40084	300	0	0	0	0	30	28	25	160139	100	160009	100	160020	500	1320129	40065	40039	40057	19977	6	20035	160122	200	160032	200	320064	40084	40058	1	1	160201	100	99	100	100	160000	100	0	3	1	1	1	10118	0	16	0	0	40035	160000	100	40074	40040	40074	40040	40058
160204	40038	300	0	0	0	0	55	70	25	160108	100	160008	100	160022	500	1280132	40019	40065	40075	19988	6	20006	160120	200	160032	200	320064	40073	40038	1	1	160201	100	99	100	100	160000	100	5	0	1	1	1	10118	0	16	0	0	40036	160000	100	40066	40039	40076	40039	40039
160204	40038	300	0	0	0	0	55	0	25	160109	100	160009	100	160020	500	5516250	40020	40084	40058	19977	6	20029	160120	200	160032	200	320064	40038	40084	1	1	160201	100	99	100	100	160000	100	53	0	1	1	1	10118	0	16	0	0	40081	160000	100	40074	40040	40074	40040	40040
160204	40039	300	0	0	0	39	56	17	25	160206	100	160009	100	160020	500	4798197	40019	40078	40084	19997	6	20035	160122	200	160032	200	320064	40039	40073	1	1	160201	100	99	100	100	160000	100	2	6	1	1	1	10118	0	16	0	0	40036	160000	100	40079	40085	40040	40085	40088
160204	40039	300	0	0	0	60	30	0	25	160108	100	160023	100	160020	500	1320129	40020	40039	40086	19982	6	20015	160122	200	160032	200	320064	40039	40073	1	1	160201	100	99	100	100	160000	100	52	0	1	1	1	10118	0	16	0	0	40081	160000	100	40074	40056	40040	40085	40039
160204	40039	300	0	0	0	45	30	0	25	160108	100	160039	100	160020	500	4918178	40020	40057	40039	19977	6	20011	160122	200	160032	200	320064	40084	40039	1	1	160201	100	99	100	100	160000	100	28	0	1	1	1	10118	0	16	0	0	40081	160000	100	40040	40040	40040	40074	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40065	299	0	0	67	0	25	160055	10	160000	10	160000	50	1280000	1	1	0	40019	40038	40098	19996	0	3	20044	160010	20	160000	20	320000	40101	40038	1	1	160021	10	9	10	10	160000	10	55	0	0	10022	8	3	1	11	16	2	1	1	6	6	40035	15	5	160000	10	40085	40039	40085	40039	40039
160024	40038	302	0	0	46	0	25	160033	10	160095	10	160000	50	1280000	0	1	5	40038	40039	40038	19997	0	3	20018	160010	20	160000	20	320000	40039	40038	1	1	160021	10	9	10	10	160000	10	1	0	0	10022	8	5	1	6	16	2	1	1	4	4	40140	15	10	160000	10	40039	40040	40039	40039	40074
160024	40038	300	0	27	45	0	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	40039	40039	20037	0	3	20019	160010	20	160000	20	320000	40087	40064	1	1	160021	10	9	10	10	160000	10	1	18	0	10024	8	5	2	4	16	2	1	1	4	4	40052	15	5	160000	10	40040	40039	40099	40040	40039
160024	40038	300	0	150	45	3	25	160038	10	160001	10	160000	50	1280000	1	1	5	40019	40038	40112	19996	0	3	20044	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	2	6	0	10022	11	6	1	4	16	2	1	1	5	6	40036	30	10	160000	10	40039	40085	40039	40040	40039
160024	40112	300	0	1	45	3	25	160010	10	160000	10	160000	50	5516100	1	1	5	40065	40084	40038	19996	0	3	20018	160010	20	160000	20	320000	40058	40084	1	1	160021	10	9	10	10	160000	10	35	0	0	10022	8	5	1	4	16	2	1	1	5	4	40060	30	5	160000	10	40039	40040	40040	40064	40040
160024	40039	300	0	68	45	0	25	160066	10	160001	10	160000	50	3997424	1	1	5	40082	40087	40039	19996	0	3	20018	160010	20	160000	20	320000	40064	40038	1	1	160021	10	9	10	10	160000	10	36	0	0	10022	8	5	1	5	16	2	1	1	6	5	40035	15	5	160000	10	40040	40039	40099	40040	40039
160024	40039	300	0	0	45	105	25	160011	10	160000	10	160000	50	1280000	1	1	5	40019	40038	40039	20029	0	3	20018	160010	20	160000	20	320000	40084	40038	1	1	160021	10	9	10	10	160000	10	1	0	0	10022	8	5	1	5	16	4	1	2	4	5	40035	15	5	160000	10	40143	40039	40039	40113	40040
160024	40039	300	0	0	616	149	25	160011	10	160060	10	160000	50	4037415	1	1	5	40019	40038	40038	20010	0	3	20018	160010	20	160000	20	320000	40038	40057	1	1	160021	10	9	10	10	160000	10	13	0	0	10022	8	5	1	5	16	2	1	1	4	3	40035	15	7	160000	10	40039	40040	40040	40039	40039
160024	40073	299	0	23	45	0	25	160010	10	160104	10	160000	50	1280000	1	1	5	40020	40038	40143	19996	0	3	20018	160010	20	160000	20	320000	40057	40084	1	1	160021	10	9	10	10	160000	10	3	6	0	10024	11	5	2	4	16	4	2	1	3	4	40081	15	5	160000	10	40039	40144	40040	40039	40091
160024	40038	300	0	60	67	0	25	160010	10	160000	10	160000	50	1319998	1	1	5	40065	40084	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40084	1	1	160021	10	9	10	10	160000	10	61	0	0	10022	8	5	1	5	16	2	1	1	5	4	40054	15	5	160000	10	40039	40085	40039	40085	40040

INS (element, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations