Firestorm: INS (general, B) measurements

Code:

  ins v0.b[2], w1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	2040	15	0	2025	1690	25	2000	1000	1000	1000	1000	6342	265147	1	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	1	0	73	2	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	16	0	2025	1690	25	2000	1000	1000	1000	1000	6342	265147	0	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	15	0	2025	1690	25	2000	1000	1000	1000	1000	6342	265147	0	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	15	0	2025	1690	25	2000	1000	1000	1000	1000	6373	265147	0	2060	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	16	0	2025	1690	25	2000	1000	1000	1000	1000	6342	265147	1	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	0	21	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	15	0	2025	1690	25	2000	1000	1000	1000	1000	6342	265147	1	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	15	0	2025	1686	25	2000	1000	1000	1000	1000	6342	265147	1	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	4	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	15	0	2025	1690	25	2000	1000	1000	1000	1000	6342	265147	1	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	15	0	2025	1690	25	2000	1000	1000	1000	1000	6342	265147	1	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	15	0	2025	1690	25	2000	1000	1000	1000	1000	6342	265147	1	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041

Test 2: Latency 1->1

Code:

  ins v0.b[2], w1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20040	161	0	0	0	0	18	0	0	20025	19689	0	37	20100	100	10000	10000	100	10000	10000	516	53518	2848132	0	20021	0	20040	20040	17175	3	17498	20100	200	10000	10170	200	10000	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	2	0	0	10000	0	1	0	0	0	0	0	0	710	1	16	1	1	20086	0	10000	10000	100	20041	20041	20041	20041	20041
20204	20040	161	0	0	0	0	0	0	0	20025	19689	0	25	20100	100	10000	10000	102	10000	10000	500	53518	2848132	0	20021	0	20040	20040	17175	3	17498	20100	200	10000	10000	200	10006	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	0	0	0	10000	0	0	0	0	0	0	0	0	710	0	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20041
20204	20040	161	0	0	0	0	0	0	0	20025	19671	0	25	20100	100	10000	10000	100	10000	10000	500	53518	2848132	0	20021	0	20040	20040	17175	3	17498	20100	200	10000	10000	200	10000	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	0	0	0	10000	0	0	0	3	0	0	0	0	739	0	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20041
20204	20090	161	0	0	0	0	297	0	0	20025	19689	0	25	20100	100	10000	10000	100	10000	10000	522	53518	2848132	0	20021	0	20040	20040	17175	3	17498	20100	200	10000	10000	200	10000	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	0	0	0	10000	0	0	0	6	0	1	0	0	710	1	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20041
20204	20040	161	0	0	0	0	120	0	0	20025	19689	0	25	20100	100	10012	10000	100	10000	10158	500	56831	2848132	0	20021	0	20040	20040	17175	3	17498	20100	200	10000	10000	200	10000	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	0	0	0	10000	0	8	0	0	0	0	0	1	710	0	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20041
20204	20040	160	0	0	0	0	0	0	0	20025	19689	0	25	20100	100	10012	10000	100	10000	10000	500	53518	2848132	0	20021	3	20040	20090	17175	26	17498	20100	200	10000	10166	200	10000	20000	20090	20040	1	1	10201	100	99	100	100	10000	100	0	0	0	10000	0	0	0	0	0	0	0	0	710	1	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20041
20204	20040	161	0	0	0	0	30	0	0	20025	19689	0	25	20100	100	10000	10000	100	10000	10000	500	53518	2848132	0	20021	0	20040	20040	17175	3	17498	20100	200	10000	10000	200	10171	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	0	0	0	10000	0	0	0	0	0	0	0	0	710	1	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20228
20204	20040	161	0	0	0	0	0	0	0	20025	19689	0	25	20100	100	10000	10000	100	10000	10000	500	53518	2848132	1	20021	0	20040	20040	17175	3	17498	20100	200	10000	10000	200	10000	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	0	0	0	10000	0	0	0	0	0	0	0	0	710	1	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20041
20204	20040	156	0	0	0	0	0	0	0	20025	19689	0	25	20100	100	10000	10000	100	10000	10000	500	53518	2848132	1	20021	0	20040	20040	17175	3	17498	20100	200	10000	10000	200	10000	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	0	0	0	10000	0	0	0	0	0	0	0	0	710	1	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20041
20204	20040	155	0	0	0	0	0	0	0	20025	19689	0	25	20100	100	10000	10000	100	10000	10000	500	53518	2848132	1	20021	0	20040	20040	17175	3	17498	20100	200	10000	10000	200	10000	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	0	0	0	10000	0	0	0	0	0	0	0	0	710	1	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20041

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20040	150	0	0	0	0	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53585	2848147	0	20021	20040	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	0	10000	0	640	3	16	3	3	20037	10000	10000	10	20041	20041	20041	20041	20041
20024	20040	150	0	0	0	0	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53585	2848147	0	20021	20040	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	0	10000	0	640	3	16	3	3	20037	10000	10000	10	20041	20041	20041	20041	20041
20024	20040	150	0	0	0	0	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53585	2848147	1	20021	20040	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	0	10000	0	640	3	16	3	3	20077	10000	10000	10	20041	20041	20041	20041	20041
20024	20040	150	0	0	0	0	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53585	2848147	1	20021	20040	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	0	10000	0	640	3	16	3	3	20037	10000	10000	10	20041	20041	20041	20041	20041
20024	20040	150	0	0	0	0	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53585	2848147	1	20021	20040	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	0	10000	0	640	3	16	3	3	20037	10000	10000	10	20041	20041	20041	20041	20041
20024	20040	150	0	0	0	0	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53585	2848147	1	20021	20040	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	0	10000	0	640	3	16	3	3	20037	10000	10000	10	20041	20041	20041	20041	20041
20024	20040	150	0	0	0	0	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53585	2848147	1	20021	20040	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	0	10000	0	640	3	16	3	3	20037	10000	10000	10	20041	20041	20041	20041	20041
20024	20040	150	0	0	0	0	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53585	2848147	1	20021	20040	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	4	10000	0	640	3	16	3	3	20037	10000	10000	10	20041	20041	20041	20041	20041
20024	20040	150	0	0	0	0	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53585	2848147	0	20021	20040	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	0	10000	0	640	3	16	3	3	20037	10000	10000	10	20041	20041	20041	20041	20041
20024	20040	150	0	0	0	0	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53585	2848147	0	20021	20040	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	0	10000	0	640	3	16	3	3	20037	10000	10000	10	20041	20041	20041	20041	20041

Test 3: Latency 1->2 roundtrip

Code:

  ins v0.b[2], w0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 12.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	c9	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	120032	899	0	0	1047	0	120017	109456	25	40100	10104	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120032	120032	115532	7	116236	30100	200	10003	20005	200	10003	30008	120032	120032	2	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	1	0	1	1	1317	0	1	16	2	2	119583	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	792	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120032	120032	115532	6	116267	30100	200	10003	20005	200	10003	30008	120032	120032	2	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	1	0	1	1	1318	0	1	16	1	1	119583	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	930	0	0	960	176	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120032	120032	115532	6	116236	30100	200	10003	20005	200	10003	30008	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	1	0	1	1	1318	0	1	17	2	2	119583	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	931	0	0	579	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120032	120032	115532	7	116235	30100	200	10003	20005	200	10003	30008	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	1	0	1	1	1318	0	1	16	1	2	119583	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	930	0	0	909	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120032	120032	115532	7	116239	30100	200	10003	20005	200	10003	30008	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	0	0	0	1310	1	3	16	3	3	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	1230	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	0	1	0	1310	1	3	16	3	3	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	726	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120032	120032	115525	3	116245	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	0	0	0	1310	1	3	16	3	3	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	1179	0	120017	109457	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	0	0	0	1310	1	3	16	3	3	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	0	0	0	1310	1	3	16	3	3	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5738190	13672169	0	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	0	0	0	1310	1	3	16	3	3	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033

1000 unrolls and 10 iterations

Result (median cycles for code): 12.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	120032	899	0	0	0	120017	109457	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	30000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	1	0	1270	0	1	16	1	1	119586	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	30000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	1295	0	1	16	1	1	119606	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	1064	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	30000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	1270	0	1	16	1	1	119602	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	120032	120038	115548	3	116262	30010	20	10000	20000	20	10000	30000	120032	120116	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	1270	0	2	16	1	1	119646	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	30000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	1270	0	1	16	1	1	119623	10000	10000	10000	10010	120033	120033	120076	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	30000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	1270	0	1	16	1	1	119606	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	30000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1	1315	0	2	16	1	1	119639	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	30000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	1270	0	1	16	1	1	119854	10000	10000	10000	10010	120033	120033	120033	120033	120131
30024	120032	899	0	0	0	120017	109455	25	40010	10010	20000	10000	10	20000	10050	50	5735960	13670029	1	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	30000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	1270	0	1	16	1	1	119624	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	6	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	30000	120033	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	1270	0	1	16	0	1	119608	10000	10000	10000	10010	120034	120033	120033	120033	120033

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  ins v0.b[2], w8
  movi v1.16b, 0
  ins v1.b[2], w8
  movi v2.16b, 0
  ins v2.b[2], w8
  movi v3.16b, 0
  ins v3.b[2], w8
  movi v4.16b, 0
  ins v4.b[2], w8
  movi v5.16b, 0
  ins v5.b[2], w8
  movi v6.16b, 0
  ins v6.b[2], w8
  movi v7.16b, 0
  ins v7.b[2], w8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3759

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240204	30094	242	0	0	12	0	30054	0	27	160143	125	80005	80013	125	80019	80019	650	416480	981487	1	30048	0	30068	30069	0	0	6	14	160163	200	80019	80019	200	80019	160038	30132	30068	1	1	160201	100	99	100	100	160000	100	0	80002	0	0	1	1	1	10119	3	16	1	1	30065	25	80000	160000	100	30069	30069	30069	30069	30070
240204	30069	241	0	0	0	0	30053	0	27	160143	125	80005	80013	125	80019	80019	650	416480	981487	0	30048	0	30068	30069	0	0	7	14	160163	200	80019	80019	200	80019	160038	30069	30156	1	1	160201	100	99	100	100	160000	100	0	80002	0	0	1	1	1	10119	2	16	1	1	30066	25	80000	160000	100	30197	30069	30069	30069	30069
240204	30069	242	0	0	0	0	30053	0	26	160143	125	80005	80013	125	80019	80019	650	416480	981487	1	30048	0	30068	30069	0	0	7	14	160163	200	80019	80019	200	80019	160038	30068	30128	1	1	160201	100	99	100	100	160000	100	0	80002	0	3	1	1	1	10119	3	16	1	1	30066	25	80000	160000	100	30069	30070	30069	30069	30070
240204	30069	241	0	0	0	0	30053	0	27	160143	125	80005	80013	125	80019	80019	650	416480	981487	1	30048	0	30068	30069	0	0	7	14	160163	200	80019	80019	200	80019	160038	30068	30068	1	1	160201	100	99	100	100	160000	100	0	80002	0	0	1	1	2	10119	1	16	1	1	30065	25	80000	160000	100	30069	30069	30070	30070	30070
240204	30069	233	0	0	0	0	30053	0	27	160143	125	80005	80013	125	80019	80019	650	416480	981487	1	30049	0	30069	30069	0	0	6	14	160163	200	80019	80019	200	80019	160038	30099	30068	2	1	160201	100	99	100	100	160000	100	0	80002	0	3	1	1	1	10119	1	16	1	1	30066	25	80000	160000	100	30069	30069	30069	30069	30069
240204	30068	233	0	0	0	0	30053	0	27	160143	125	80005	80013	125	80019	80019	650	416480	981487	1	30048	0	30068	30068	0	0	7	14	160163	200	80019	80019	200	80019	160038	30068	30069	1	1	160201	100	99	100	100	160000	100	0	80002	0	0	1	1	1	10119	1	16	1	1	30161	25	80000	160000	100	30070	30069	30070	30070	30069
240204	30068	241	0	0	0	0	30053	0	27	160143	125	80005	80014	125	80019	80158	650	417492	983437	1	30048	0	30068	30069	0	0	7	14	160163	200	80024	80023	200	80024	160046	30081	30081	1	1	160201	100	99	100	100	160000	100	0	80002	0	0	1	1	1	10119	1	16	1	1	30065	25	80000	160000	100	30069	30070	30070	30070	30070
240204	30069	241	5	0	15	0	30053	0	27	160143	125	80005	80013	125	80019	80019	650	416480	981487	1	30048	0	30069	30068	0	0	6	14	160163	200	80019	80019	200	80019	160038	30068	30068	1	1	160201	100	99	100	100	160000	100	0	80002	0	0	1	1	1	10119	1	16	1	1	30066	25	80000	160000	100	30070	30070	30070	30070	30069
240204	30069	241	0	0	0	0	30054	0	26	160144	125	80005	80013	125	80019	80019	650	415885	981487	0	30048	0	30068	30068	0	0	7	14	160163	200	80019	80019	200	80019	160038	30068	30068	1	1	160201	100	99	100	100	160000	100	0	80002	0	0	1	1	1	10119	1	16	1	1	30066	25	80000	160000	100	30069	30069	30069	30070	30070
240204	30068	242	0	0	0	0	30054	0	27	160143	125	80005	80013	125	80019	80019	650	416480	981487	1	30048	0	30069	30068	0	0	7	14	160163	200	80019	80019	200	80019	160038	30069	30069	1	1	160201	100	99	100	100	160000	100	0	80002	0	3	1	2	2	10129	1	16	1	1	30065	25	80000	160000	100	30070	30069	30069	30070	30069

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3756

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240024	30063	225	0	0	0	0	0	0	30030	0	26	160012	12	80000	80000	12	80000	80000	62	401157	960991	1	1	10	30026	30045	30045	0	3	24	160012	20	80000	80000	20	80000	160000	30045	30045	1	1	160021	10	9	10	10	160000	10	0	0	80000	0	0	0	0	10022	13	2	1	9	19	2	1	1	2	3	30042	2	20	0	80000	160000	10	30046	30046	30046	30046	30046
240024	30045	225	0	0	0	0	0	0	31056	256	374	162609	13	80519	81170	11	81238	81222	62	444672	1021517	1	1	10	30935	31155	31044	238	179	606	162523	20	81225	81354	20	80422	162460	31170	31165	10	1	160021	10	9	10	10	160000	10	0	25	81166	1	0	6403	0	10022	13	5	1	7	22	2	1	1	4	3	30042	2	20	0	80000	160000	10	30046	30046	30046	30046	30787
240024	30510	225	0	1	5	4	810	352	30030	160	315	161573	10	80390	80650	12	80827	80410	68	451506	1022183	1	1	10	30485	30413	30574	358	122	216	160012	20	80000	80812	20	80000	160000	30045	30666	3	1	160021	10	9	10	10	160000	10	0	9	80000	0	2	0	0	10278	13	5	1	9	146	2	1	2	4	5	31501	1	20	0	80000	160000	10	31910	31541	32028	31384	31047
240024	30045	233	0	1	0	0	0	0	30030	0	26	160012	12	80000	80000	12	80000	80000	62	401157	960991	0	1	10	30026	30045	30045	0	3	24	160012	20	80000	80000	20	80000	160000	30045	30072	1	1	160021	10	9	10	10	160000	10	0	0	80000	1	0	0	0	10024	16	6	2	9	19	2	1	1	3	3	30042	2	20	0	80000	160000	10	30046	30046	30046	30046	30046
240024	30045	225	0	0	0	0	0	0	30030	0	26	160012	12	80000	80000	12	80000	80000	62	407760	969795	0	1	10	30026	30045	30136	0	3	24	160012	20	80000	80000	20	80000	160000	30045	30058	1	1	160021	10	9	10	10	160000	10	0	0	80000	0	0	0	0	10024	13	5	1	10	22	2	1	2	2	3	30042	2	20	0	80000	160000	10	30046	30046	30046	30046	30046
240024	30045	225	0	0	0	0	0	0	30030	0	26	160012	12	80000	80000	12	80000	80000	62	407760	969795	0	1	10	30026	30045	30045	0	3	24	160012	20	80000	80000	20	80000	160000	30045	30054	1	1	160021	10	9	10	10	160000	10	0	0	80000	0	0	0	0	10024	13	6	2	8	22	4	2	2	3	2	30042	2	40	0	80000	160000	10	30046	30046	30046	30046	30046
240024	30045	225	0	0	0	0	0	0	30030	0	26	160012	12	80000	80000	12	80000	80000	62	407760	969795	0	1	10	30026	30045	30045	0	3	24	160012	20	80000	80000	20	80000	160000	30045	30045	1	1	160021	10	9	10	10	160000	10	0	0	80000	0	0	0	0	10022	13	5	1	6	19	4	2	2	3	3	30042	2	40	0	80000	160000	10	30046	30046	30046	30046	30046
240024	30045	225	0	0	0	0	0	0	30030	0	26	160012	12	80000	80000	12	80000	80000	62	407760	969795	0	1	10	30026	30045	30045	0	3	24	160012	20	80000	80000	20	80000	160000	30045	30045	1	1	160021	10	9	10	10	160000	10	0	0	80000	0	0	0	0	10022	13	5	1	7	19	4	2	2	2	3	30042	2	40	0	80000	160000	10	30046	30046	30046	30046	30046
240024	30045	225	0	0	0	0	0	0	30030	0	26	160012	12	80000	80000	12	80000	80000	62	407760	960991	1	1	10	30026	30045	30045	0	3	24	160012	20	80000	80000	20	80000	160000	30047	30045	1	1	160021	10	9	10	10	160000	10	0	0	80000	0	0	0	0	10022	13	5	1	6	19	2	1	1	3	2	30042	2	20	0	80000	160000	10	30046	30046	30046	30046	30046
240024	30045	233	0	0	0	0	0	0	30030	0	26	160012	12	80000	80000	12	80000	80000	62	401157	960991	1	1	10	30026	30045	30045	0	3	24	160012	20	80000	80000	20	80000	160000	30045	30091	1	1	160021	10	9	10	10	160000	10	0	0	80000	0	0	0	0	10022	13	5	1	7	22	2	1	1	2	3	30042	2	20	0	80000	160000	10	30046	30046	30046	30046	30132

INS (general, B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations