Firestorm: INS (general, H) measurements

Code:

  ins v0.h[2], w1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	2040	15	0	2025	1690	25	2000	1000	1000	1000	1000	6342	265147	1	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	16	0	2025	1690	25	2000	1000	1000	1000	1000	6342	265147	1	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	17	0	2025	1690	25	2000	1000	1000	1000	1000	6342	265147	1	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	15	0	2025	1690	25	2000	1000	1000	1000	1000	6342	265147	1	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	16	0	2025	1690	25	2000	1000	1000	1000	1000	6342	265147	0	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	16	0	2025	1690	25	2000	1000	1000	1000	1000	6347	265147	0	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	16	0	2025	1690	25	2000	1000	1000	1000	1000	6342	265147	0	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	15	0	2025	1690	25	2000	1000	1000	1000	1000	6342	265147	1	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	16	0	2025	1690	25	2000	1000	1000	1000	1000	6342	265147	1	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	1	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	16	0	2025	1690	25	2000	1000	1000	1152	1000	6342	265147	1	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	0	39	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041

Test 2: Latency 1->1

Code:

  ins v0.h[2], w1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20040	155	1	0	0	0	0	0	20025	19689	25	20100	100	10000	10000	100	10000	10000	500	53746	2848132	1	20021	0	20040	20040	17175	3	17498	20100	200	10000	10000	200	10000	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	0	0	182	10000	1	0	0	0	0	0	710	1	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20041
20204	20040	155	0	0	0	0	132	0	20025	19689	25	20100	100	10000	10000	100	10000	10000	500	53518	2848132	1	20021	0	20040	20040	17175	3	17498	20100	200	10000	10000	200	10000	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	0	0	0	10000	0	0	0	0	0	0	710	1	16	2	2	20037	0	10000	10000	100	20041	20041	20041	20041	20041
20204	20040	155	0	0	0	0	0	0	20025	19689	25	20100	100	10000	10000	100	10000	10000	500	53518	2848132	1	20021	0	20040	20040	17175	3	17498	20100	200	10000	10000	200	10000	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	0	0	0	10000	0	0	0	0	0	0	710	1	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20041
20204	20040	155	0	0	0	0	0	0	20025	19689	25	20100	100	10000	10000	100	10000	10000	500	53522	2848132	1	20021	0	20040	20040	17175	3	17498	20100	200	10000	10000	200	10000	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	0	0	0	10000	0	0	0	0	0	0	710	1	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20041
20204	20040	155	0	0	0	0	0	0	20025	19689	25	20100	100	10000	10000	100	10000	10000	500	53518	2848132	1	20021	0	20040	20040	17175	3	17498	20100	200	10000	10000	200	10000	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	0	0	0	10000	0	0	0	3	0	0	710	1	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20165
20204	20040	155	0	0	0	0	0	0	20025	19689	25	20100	100	10000	10000	100	10000	10000	500	53518	2848132	1	20021	0	20040	20040	17175	3	17498	20100	200	10000	10000	200	10000	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	0	0	0	10000	0	23	0	0	0	0	710	1	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20041
20204	20040	155	0	0	0	0	0	0	20025	19689	25	20100	100	10000	10000	100	10000	10000	500	53518	2848132	1	20021	0	20040	20040	17175	3	17499	20100	200	10000	10000	200	10000	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	0	0	0	10000	0	47	0	3	0	0	710	1	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20041
20204	20040	156	0	0	0	0	0	0	20025	19689	25	20100	100	10000	10000	100	10000	10000	500	53518	2848132	1	20021	0	20040	20040	17175	3	17498	20100	200	10000	10000	200	10000	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	0	0	0	10000	0	0	0	0	0	0	710	1	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20041
20204	20040	155	0	0	0	0	0	0	20025	19689	25	20100	100	10000	10000	100	10000	10000	500	53518	2849566	1	20021	0	20040	20040	17175	3	17498	20100	200	10000	10000	200	10000	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	0	0	0	10000	0	0	0	0	0	0	710	1	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20041
20204	20040	155	0	0	0	0	0	0	20025	19689	25	20100	100	10000	10000	100	10000	10000	500	53518	2848132	1	20021	0	20040	20040	17175	3	17498	20100	200	10000	10000	200	10000	20000	20040	20040	2	1	10201	100	99	100	100	10000	100	0	0	0	10000	0	0	0	0	0	0	710	1	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20041

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20040	155	0	0	0	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53585	2848147	1	20021	20040	20102	17184	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	10000	0	0	0	640	3	16	2	2	20037	0	10000	10000	10	20041	20041	20041	20041	20041
20024	20040	155	0	0	0	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53604	2848147	0	20021	20040	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	10000	0	0	0	640	2	16	2	2	20037	0	10000	10000	10	20041	20041	20041	20041	20041
20024	20040	155	0	0	0	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53597	2848147	1	20021	20043	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	10000	1	0	0	640	2	16	2	2	20037	0	10000	10000	10	20041	20041	20041	20041	20041
20024	20040	156	0	0	12	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53601	2848147	1	20021	20040	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	10000	0	0	0	640	2	16	2	2	20037	0	10000	10000	10	20041	20041	20041	20041	20041
20024	20040	162	0	0	0	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53589	2848147	1	20021	20040	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	10000	0	0	0	640	2	16	2	2	20037	0	10000	10000	10	20041	20041	20041	20041	20041
20024	20040	155	0	1	0	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53585	2848147	1	20021	20040	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	10000	0	0	0	640	2	16	2	2	20037	0	10000	10000	10	20041	20041	20041	20041	20041
20024	20040	156	0	0	0	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53590	2848147	1	20021	20040	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	10000	0	0	0	640	2	16	2	2	20037	0	10000	10000	10	20041	20041	20041	20041	20041
20024	20040	155	0	0	24	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53593	2848147	1	20021	20040	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	10000	0	0	0	640	2	16	2	2	20037	0	10000	10000	10	20041	20041	20041	20041	20041
20024	20040	155	0	0	0	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53612	2848147	0	20021	20040	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	10000	0	0	0	640	2	16	2	2	20037	0	10000	10000	10	20041	20041	20041	20041	20041
20024	20040	155	0	0	0	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53585	2848147	1	20021	20040	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	10000	0	0	0	640	2	16	2	2	20037	0	10000	10000	10	20041	20041	20041	20041	20041

Test 3: Latency 1->2 roundtrip

Code:

  ins v0.h[2], w0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 12.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	120032	899	0	0	0	0	885	352	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	120032	120032	115525	3	116245	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	1310	1	2	16	2	2	119574	10007	10000	10000	10100	120033	120033	120033	120033	120041
30204	120032	899	0	0	0	0	882	0	0	120018	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120046
30204	120032	899	0	0	0	0	285	0	0	120017	109456	25	40100	10100	20000	10000	102	20000	10000	500	5735672	13679178	0	120013	120033	120033	115525	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120036	120040	120033	120033	120033
30204	120032	899	0	0	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	1310	1	2	16	0	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	225	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	1310	1	2	16	2	3	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	1	0	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	120032	120032	115525	3	116242	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	1310	0	3	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033

1000 unrolls and 10 iterations

Result (median cycles for code): 12.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	bb	c2	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	120032	900	0	0	0	0	0	6	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	120032	120075	115550	3	116262	30010	20	10000	20000	20	10000	30000	120032	120032	1	1	20021	10	9	10	10010	0	10000	10	0	10000	0	0	4049	0	0	1270	2	16	0	1	2	119576	10056	10000	10000	10010	122220	122732	122597	122221	122640
30024	122341	919	0	0	1	33	27	4236	2464	120017	109456	25	40010	10010	20000	10000	18	24410	11735	61	5830104	13847798	0	122613	123478	123291	116885	164	117632	34499	20	10000	20000	20	10000	30000	120032	120032	2	1	20021	10	9	10	11334	0	10000	10	0	10003	3	2	0	0	0	1270	1	16	0	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	0	0	15	624	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	120059	120057	115548	3	116262	30010	20	10000	20000	20	10000	30184	120032	120032	1	1	20021	10	9	10	10010	0	10000	10	0	10000	1	0	0	0	0	1270	1	16	0	1	1	119574	10000	10000	10000	10010	120033	120033	120069	120084	120033
30024	120032	899	0	0	0	0	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	120097	120385	115551	3	116262	30010	20	10000	20000	20	10000	30000	120032	120032	1	1	20021	10	9	10	10010	0	10000	10	0	10000	1	0	0	0	0	1270	1	16	0	1	2	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	0	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	120127	120033	115548	3	116262	30010	20	10000	20000	20	10000	30000	120032	120032	1	1	20021	10	9	10	10010	0	10000	10	0	10000	0	0	0	0	0	1270	1	16	0	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	0	0	0	0	120018	109456	25	40010	10012	20000	10002	10	20000	10000	50	5735672	13676340	0	121433	122396	121597	116336	3	116262	30010	20	10000	20123	20	10000	30551	120205	120200	26	1	20021	10	9	10	10010	0	10000	10	0	10045	0	4	119495	0	0	1270	2	16	0	3	6	121103	10044	10000	10000	10010	120034	120034	120033	120033	122310
30024	122405	914	3	1	0	0	0	0	0	120017	110375	622	40216	10064	20108	10060	14	23154	11294	66	5802140	13822211	0	120013	120032	120112	115552	3	116262	30345	20	11419	22067	22	11292	33109	121949	121812	27	1	20021	10	9	10	10010	0	10000	10	2	10040	1	4	111450	0	0	1415	1	33	0	2	3	119574	10000	10000	10000	10010	120033	120034	120033	120033	122399
30024	122674	954	0	0	0	1	0	0	0	120017	109456	25	40010	10010	20004	10000	10	20119	10000	50	5735672	13674000	0	120013	120041	120092	115548	3	116262	30010	20	10000	20000	20	10000	30000	120032	120032	1	1	20021	10	9	10	10010	0	10000	10	0	10000	0	0	3	0	0	1270	1	16	0	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	0	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120099	120032	120085	115658	3	116262	30010	20	10000	20000	20	10000	30000	120032	120032	1	1	20021	10	9	10	10010	0	10000	10	0	10000	0	0	0	0	0	1270	1	16	0	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	0	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	120032	120069	115551	3	116262	30010	20	10000	20000	20	10000	30000	120032	120032	1	1	20021	10	9	10	10010	0	10000	10	0	10000	0	0	0	0	0	1270	1	16	0	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  ins v0.h[2], w8
  movi v1.16b, 0
  ins v1.h[2], w8
  movi v2.16b, 0
  ins v2.h[2], w8
  movi v3.16b, 0
  ins v3.h[2], w8
  movi v4.16b, 0
  ins v4.h[2], w8
  movi v5.16b, 0
  ins v5.h[2], w8
  movi v6.16b, 0
  ins v6.h[2], w8
  movi v7.16b, 0
  ins v7.h[2], w8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3759

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240204	30097	234	0	0	30054	0	26	160142	125	80005	80013	125	80019	80019	650	416480	981487	0	30048	30069	30069	6	14	160163	200	80019	80019	200	80019	160038	30069	30069	1	1	160201	100	99	100	100	160000	100	0	80002	0	0	1	1	1	10118	1	16	30066	25	80000	160000	100	30070	30070	30070	30069	30069
240204	30069	233	0	0	30053	0	27	160143	125	80005	80013	125	80019	80019	650	416480	981487	0	30048	30068	30069	6	14	160163	200	80019	80019	200	80019	160038	30068	30068	1	1	160201	100	99	100	100	160000	100	0	80002	0	0	1	1	1	10118	0	16	30066	25	80000	160000	100	30069	30069	30069	30070	30069
240204	30069	233	0	0	30054	0	27	160143	125	80005	80013	125	80019	80019	650	416480	983206	0	30048	30068	30069	7	14	160163	200	80019	80019	200	80019	160038	30068	30068	1	1	160201	100	99	100	100	160000	100	0	80002	0	0	1	1	1	10119	0	16	30065	25	80000	160000	100	30069	30069	30069	30069	30069
240204	30068	233	0	0	30053	0	27	160143	125	80005	80013	125	80019	80019	650	416480	981487	0	30048	30219	30206	7	14	160163	200	80019	80019	200	80019	160038	30068	30069	1	1	160201	100	99	100	100	160000	100	0	80002	0	0	1	1	1	10119	0	16	30065	25	80000	160000	100	30069	30069	30069	30069	30069
240204	30069	233	0	0	30053	0	27	160143	125	80005	80013	125	80019	80019	650	416480	981487	0	30048	30069	30068	7	14	160163	200	80019	80019	200	80020	160038	30069	30069	1	1	160201	100	99	100	100	160000	100	0	80002	0	0	1	1	1	10118	0	16	30065	25	80000	160000	100	30070	30069	30069	30070	30070
240204	30068	233	0	0	30053	0	27	160143	125	80005	80013	125	80019	80019	650	416480	981487	1	30048	30068	30068	6	14	160163	200	80019	80019	200	80019	160038	30068	30068	1	1	160201	100	99	100	100	160000	100	0	80002	0	0	1	1	1	10119	0	16	30066	25	80000	160000	100	30070	30070	30069	30070	30070
240204	30069	233	0	0	30054	0	27	160143	125	80005	80013	125	80019	80019	650	416480	981487	0	30048	30068	30068	7	14	160163	200	80019	80019	200	80019	160038	30068	30068	1	1	160201	100	99	100	100	160000	100	0	80002	0	0	1	1	1	10118	0	16	30065	25	80000	160000	100	30069	30069	30069	30070	30069
240204	30069	233	0	0	30054	0	26	160143	125	80005	80013	125	80019	80019	650	416480	981487	0	30048	30068	30068	7	14	160163	200	80019	80019	200	80019	160038	30069	30068	1	1	160201	100	99	100	100	160000	100	0	80002	2	0	1	1	1	10119	0	16	30066	25	80000	160000	100	30069	30070	30069	30070	30069
240204	30069	233	0	0	30053	0	27	160143	125	80005	80013	125	80019	80019	650	416480	981487	0	30048	30205	30069	7	14	160163	200	80019	80019	200	80019	160038	30068	30068	1	1	160201	100	99	100	100	160000	100	0	80002	0	0	1	1	1	10118	0	16	30066	25	80000	160000	100	30069	30070	30070	30070	30070
240204	30068	233	0	0	30054	0	26	160143	125	80006	80014	125	80019	80019	650	417211	981487	0	30048	30069	30068	7	14	160163	200	80019	80019	200	80019	160038	30069	30068	1	1	160201	100	99	100	100	160000	100	0	80002	1	3	1	1	1	10119	0	16	30066	25	80000	160000	100	30070	30069	30069	30070	30069

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3756

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	c9	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240024	30046	225	0	1	0	0	0	0	0	0	30030	0	26	160013	13	80000	80000	13	80000	80000	68	401606	960901	1	1	10	30026	30045	30045	0	3	24	160013	20	80000	80000	20	80000	160000	30045	30045	1	1	160021	10	9	10	10	160000	10	0	80000	0	0	0	0	0	0	10023	16	6	1	20	52	4	2	2	18	13	30042	3	30	0	80000	160000	10	30046	30046	30046	30046	30046
240024	30045	225	0	0	0	0	0	0	0	0	30030	0	26	160013	13	80000	80000	13	80000	80000	68	401606	960901	1	1	10	30026	30045	30045	0	3	24	160013	20	80000	80000	20	80000	160000	30045	30045	1	1	160021	10	9	10	10	160000	10	0	80000	0	0	0	0	0	0	10021	13	5	1	18	17	2	1	1	18	18	30042	3	15	0	80000	160000	10	30046	30046	30424	30046	30046
240024	30045	225	0	0	0	0	0	0	0	0	30030	0	62	160013	13	80000	80000	13	80000	80000	68	401606	960901	1	1	10	30026	30045	30045	0	3	303	160013	20	80000	80000	20	80000	160000	30045	30045	1	1	160021	10	9	10	10	160000	10	0	80000	0	0	0	0	0	0	10021	13	5	1	18	17	2	1	1	18	17	30042	3	15	0	80000	160000	10	30046	30046	30046	30133	30046
240024	30045	225	0	0	0	0	0	0	0	0	30030	0	26	160013	13	80000	80000	13	80000	80000	68	401606	960901	1	1	10	30026	30045	30045	0	3	24	160013	20	80000	80000	20	80000	160000	30045	30045	1	1	160021	10	9	10	10	160000	10	0	80000	0	0	0	0	0	0	10021	13	5	1	18	17	2	1	1	15	19	30042	3	15	0	80000	160000	10	30046	30046	30046	30046	30046
240024	30045	225	0	0	0	0	0	0	0	0	30030	0	26	160013	13	80000	80000	13	80000	80000	68	401606	960901	1	1	10	30026	30045	30045	0	3	24	160013	20	80000	80000	20	80000	160000	30045	30168	1	1	160021	10	9	10	10	160000	10	0	80000	0	0	0	0	0	0	10021	13	6	1	16	17	2	1	1	17	18	30042	3	30	0	80000	160000	10	30046	30046	30046	30046	30046
240024	30045	225	0	0	0	0	0	0	0	0	30030	0	26	160013	13	80000	80000	13	80000	80000	68	401606	960901	1	1	10	30088	30045	30045	0	3	24	160013	20	80000	80000	20	80000	160000	30045	30045	1	1	160021	10	9	10	10	160000	10	0	80000	0	0	0	0	0	0	10021	13	5	1	17	17	2	1	1	12	19	30042	3	15	0	80000	160000	10	30046	30046	30046	30046	30046
240024	30045	225	0	0	0	0	0	0	0	0	30030	531	26	160013	13	80000	80000	13	80000	80000	68	401606	960901	1	1	10	30026	30045	30045	0	3	24	160013	20	80000	80000	20	80000	160000	30045	30045	1	1	160021	10	9	10	10	160000	10	0	80000	0	0	0	0	0	0	10023	16	7	2	17	17	4	2	2	18	19	30042	3	30	0	80000	160000	10	30046	30046	30046	30046	30046
240024	30045	225	0	0	0	0	0	0	0	0	30030	0	26	160013	13	80000	80000	13	80000	80000	68	401606	960901	0	1	10	30026	30045	30045	0	3	24	160013	20	80000	80000	20	80000	160000	30045	30045	1	1	160021	10	9	10	10	160000	10	0	80000	0	0	0	0	0	0	10023	16	7	2	17	17	4	2	2	16	11	30042	3	30	0	80000	160000	10	30046	30046	30046	30046	30046
240024	30045	225	0	0	0	0	0	0	0	0	30030	0	26	160013	13	80000	80000	13	80000	80000	68	401606	960901	0	1	10	30026	30044	30045	0	3	24	160013	20	80000	80000	20	80000	160000	30045	30045	1	1	160021	10	9	10	10	160000	10	0	80000	0	0	0	0	0	0	10023	16	7	2	16	17	4	2	2	18	17	30042	3	30	0	80000	160000	10	30046	30046	30046	30046	30046
240024	30045	225	0	0	0	0	0	0	0	0	30030	0	26	160013	13	80000	80000	13	80000	80000	68	401606	960901	0	1	10	30029	30045	30045	0	3	24	160013	20	80000	80000	20	80000	160000	30045	30045	1	1	160021	10	9	10	10	160000	10	0	80000	0	0	0	0	0	0	10021	13	6	1	15	17	2	1	1	17	16	30042	3	15	0	80000	160000	10	30046	30046	30046	30046	30046

INS (general, H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations