Firestorm: INS (general, S) measurements

Code:

  ins v0.s[2], w1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	4f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb access (a0)	l1d tlb miss (a1)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	2040	15	0	0	0	0	0	0	2025	1690	0	25	2000	1000	1000	1000	1000	6342	265147	1	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	0	0	0	1000	0	0	0	0	0	73	2	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	16	0	0	0	0	12	0	2025	1690	0	25	2000	1000	1000	1000	1000	6342	265147	1	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	0	0	0	1000	0	0	0	39	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	16	0	0	0	0	0	0	2025	1690	0	25	2000	1000	1000	1000	1000	6346	265147	1	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	0	0	0	1000	0	0	0	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	16	0	0	0	0	12	0	2025	1690	0	25	2000	1000	1000	1000	1000	6342	265147	0	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	0	0	0	1000	0	0	0	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	16	0	0	0	0	0	0	2025	1690	0	25	2000	1000	1000	1000	1000	6342	265147	0	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	0	0	0	1000	0	0	0	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	16	0	0	0	0	0	0	2025	1690	0	25	2000	1000	1000	1000	1000	6342	265147	0	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	0	0	0	1000	0	0	0	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	16	0	0	0	0	0	0	2025	1690	0	25	2000	1000	1000	1000	1000	6342	265147	0	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	0	0	0	1000	0	0	0	21	0	73	1	16	1	1	2037	1000	1000	2041	2041	2042	2041	2041
2004	2040	15	0	0	0	0	0	0	2025	1690	0	25	2000	1000	1000	1000	1000	6346	265147	0	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	0	0	0	1000	0	0	0	36	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	16	0	0	0	0	0	0	2025	1690	0	25	2000	1000	1000	1000	1000	6342	265147	0	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	0	0	0	1000	0	0	0	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	17	0	0	0	0	0	0	2025	1690	0	25	2000	1000	1000	1000	1000	6377	265147	0	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	0	0	0	1000	0	0	0	9	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041

Test 2: Latency 1->1

Code:

  ins v0.s[2], w1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20040	155	0	0	0	0	0	20025	19680	0	55	20100	100	10000	10000	100	10000	10000	500	53534	2848132	20021	20040	20040	17175	3	17498	20100	200	10000	10000	200	10000	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	10000	0	21	710	2	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20041
20204	20040	155	0	0	0	0	0	20025	19689	0	25	20100	100	10000	10000	100	10000	10000	500	53534	2848132	20021	20040	20040	17175	3	17498	20100	200	10000	10000	200	10000	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	10000	0	0	710	1	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20041
20204	20040	155	0	0	0	0	0	20025	19689	0	25	20100	100	10000	10000	100	10000	10000	500	53518	2848132	20021	20040	20040	17175	3	17498	20100	200	10000	10000	200	10000	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	10000	0	21	710	0	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20041
20204	20040	155	0	0	0	0	0	20025	19689	0	25	20100	100	10000	10000	100	10000	10000	500	53579	2848132	20021	20040	20040	17175	3	17498	20100	200	10000	10000	200	10000	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	10000	0	18	710	1	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20041
20204	20040	155	0	0	0	0	0	20025	19689	0	25	20100	100	10000	10000	100	10000	10000	500	53518	2848132	20021	20040	20040	17175	3	17498	20100	200	10000	10000	200	10000	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	10000	0	0	710	1	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20041
20204	20040	155	1	0	0	0	0	20025	19689	0	25	20100	100	10000	10000	100	10000	10000	500	53518	2848132	20021	20040	20040	17175	3	17498	20100	200	10000	10000	200	10000	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	10000	0	18	710	1	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20041
20204	20040	155	0	0	0	0	0	20025	19689	0	25	20100	100	10000	10000	100	10000	10000	500	53518	2848132	20021	20040	20040	17175	3	17498	20100	200	10000	10000	200	10000	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	10000	0	12	710	1	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20041
20204	20040	155	0	0	0	0	0	20025	19689	0	25	20100	100	10000	10000	100	10000	10000	500	53522	2848132	20021	20040	20040	17175	3	17498	20100	200	10000	10000	200	10000	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	10000	0	24	710	1	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20041
20204	20040	155	0	0	0	0	0	20025	19689	0	25	20100	100	10000	10000	100	10000	10000	500	53579	2848132	20021	20040	20040	17175	3	17498	20100	200	10000	10000	200	10000	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	10000	0	12	710	1	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20041
20204	20040	155	0	0	0	0	0	20025	19689	0	25	20100	100	10000	10000	100	10000	10000	500	53522	2848132	20021	20040	20040	17175	3	17498	20100	200	10000	10000	200	10000	20000	20040	20040	1	1	10201	100	99	100	100	10000	100	10000	0	18	710	1	16	1	1	20037	0	10000	10000	100	20041	20041	20041	20041	20041

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20040	155	0	0	0	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53754	2848147	0	0	20021	20040	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	10000	0	12	0	0	640	3	16	2	2	20037	0	10000	10000	10	20041	20041	20041	20041	20041
20024	20040	156	0	0	0	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53596	2848147	0	0	20021	20040	20040	17198	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	10000	0	3	0	0	640	2	16	2	2	20037	0	10000	10000	10	20041	20041	20041	20041	20041
20024	20040	155	0	0	0	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53598	2848147	0	0	20021	20040	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	10000	0	15	0	0	640	2	16	2	2	20037	0	10000	10000	10	20041	20041	20041	20041	20041
20024	20040	155	0	0	0	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53585	2848147	0	0	20021	20040	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	10000	0	0	1	0	640	2	16	2	2	20037	0	10000	10000	10	20041	20041	20041	20041	20041
20024	20040	155	0	0	12	20025	19682	84	20010	10	10000	10000	10	10000	10000	50	53586	2848147	0	0	20021	20040	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	10000	0	12	0	0	640	2	16	2	2	20037	0	10000	10000	10	20041	20041	20041	20041	20041
20024	20040	155	0	0	0	20025	19690	25	20010	10	10000	10000	10	10150	10000	50	53594	2848147	0	0	20021	20040	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	10000	0	9	0	0	640	2	17	2	2	20037	0	10000	10000	10	20041	20041	20041	20041	20041
20024	20040	155	0	0	0	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53594	2848147	0	0	20021	20040	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	10000	0	63	0	0	640	2	16	2	2	20037	0	10000	10000	10	20041	20041	20041	20041	20041
20024	20040	155	0	0	0	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53835	2848147	0	0	20021	20040	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	10000	0	12	0	0	640	2	16	2	2	20037	0	10000	10000	10	20041	20041	20041	20041	20041
20024	20040	155	0	0	0	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53585	2848147	0	0	20021	20040	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	10000	2	9	0	0	640	2	16	2	2	20037	0	10000	10000	10	20041	20041	20041	20041	20041
20024	20040	155	2	0	21	20025	19690	25	20010	10	10000	10000	10	10000	10000	50	53585	2848147	0	0	20021	20040	20040	17197	3	17520	20010	20	10000	10000	20	10000	20000	20040	20040	1	1	10021	10	9	10	10	10000	10	10000	0	0	0	0	640	2	16	2	2	20037	0	10000	10000	10	20041	20041	20041	20041	20041

Test 3: Latency 1->2 roundtrip

Code:

  ins v0.s[2], w0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 12.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	0f	19	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	120032	899	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120026	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	120017	109456	25	40100	10100	20000	10002	100	20000	10000	500	5737496	13672053	1	120014	120032	120038	115530	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	120023	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120071	120089
30204	120032	899	0	0	0	0	120017	109456	25	40109	10100	20000	10000	100	20000	10000	500	5735864	13672053	1	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120118
30204	120111	899	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	1	3	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033

1000 unrolls and 10 iterations

Result (median cycles for code): 12.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	120037	931	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	30000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1270	3	16	3	4	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	30000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1270	3	16	3	3	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	30000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1270	3	16	3	3	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	0	120032	120033	115548	3	116262	30010	20	10000	20000	20	10000	30000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	1	0	0	0	0	0	1270	4	16	3	3	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	30196	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1270	3	16	3	3	119574	10000	10000	10000	10010	120066	120033	120074	120033	120037
30025	120066	1091	0	0	0	120017	109456	40	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	30000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1270	4	16	3	3	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	6	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	3	120032	120032	115548	3	116265	30010	20	10000	20000	20	10000	30000	120047	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1270	3	16	3	3	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	30000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1270	3	16	4	3	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	1	0	2	120057	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	30000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1270	3	16	3	3	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	30000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1270	3	16	3	3	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  ins v0.s[2], w8
  movi v1.16b, 0
  ins v1.s[2], w8
  movi v2.16b, 0
  ins v2.s[2], w8
  movi v3.16b, 0
  ins v3.s[2], w8
  movi v4.16b, 0
  ins v4.s[2], w8
  movi v5.16b, 0
  ins v5.s[2], w8
  movi v6.16b, 0
  ins v6.s[2], w8
  movi v7.16b, 0
  ins v7.s[2], w8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3759

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	l1d tlb miss nonspec (c1)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240204	30095	242	1	279	30066	22	28	160153	126	80010	80017	126	80305	80024	656	423186	988422	0	0	30251	30081	30212	9	13	160173	200	80024	80023	200	80024	160046	30081	30081	1	1	160201	100	99	100	100	160000	100	0	0	80007	3	0	0	2	2	2	10128	1	23	0	1	1	30079	26	80000	160000	100	30083	30082	30083	30082	30083
240204	30082	233	0	0	30067	7	28	160153	126	80010	80017	126	80023	80024	656	416269	981215	0	0	30061	30081	30081	10	13	160173	200	80024	80023	200	80024	160046	30082	30081	1	1	160201	100	99	100	100	160000	100	0	0	80007	0	21	0	2	2	2	10129	1	23	0	1	1	30078	26	80000	160000	100	30082	30083	30082	30083	30082
240204	30081	233	0	0	30067	32	28	160153	126	80010	80017	126	80023	80024	656	416269	981215	0	1	30061	30081	30081	9	13	160173	200	80024	80023	200	80024	160046	30082	30081	1	1	160201	100	99	100	100	160000	100	0	0	80007	0	0	0	2	2	2	10155	1	23	0	1	1	30079	26	80000	160000	100	30082	30082	30082	30082	30082
240204	30081	233	0	0	30066	1	27	160153	126	80010	80017	126	80023	80024	656	416269	981215	0	0	30061	30081	30081	9	13	160173	200	80024	80023	200	80024	160046	30081	30081	1	1	160201	100	99	100	100	160000	100	0	0	80007	2	0	0	2	2	2	10129	1	23	0	1	1	30079	26	80000	160000	100	30333	30083	30083	30082	30453
240204	30082	233	0	12	30066	0	27	160153	126	80010	80017	126	80023	80024	656	417037	981698	0	0	30061	30081	30081	10	13	160173	200	80024	80023	200	80024	160046	30081	30081	1	1	160201	100	99	100	100	160000	100	0	0	80007	0	0	0	2	2	2	10128	1	23	0	1	1	30079	26	80000	160000	100	30084	30082	30082	30105	30083
240204	30081	233	0	0	30067	0	26	160153	126	80010	80017	126	80023	80024	656	416269	981215	0	1	30061	30081	30081	10	13	160173	200	80024	80023	200	80024	160046	30081	30081	1	1	160201	100	99	100	100	160000	100	0	0	80002	0	0	0	1	1	1	10119	0	16	0	0	0	30065	25	80000	160000	100	30070	30070	30069	30070	30070
240204	30069	233	0	0	30054	0	26	160143	125	80005	80013	125	80019	80019	650	416480	981487	0	0	30048	30069	30068	6	14	160163	200	80019	80019	200	80019	160038	30069	30068	1	1	160201	100	99	100	100	160000	100	0	0	80002	0	0	0	1	1	1	10118	0	16	0	0	0	30066	25	80000	160000	100	30069	30069	30089	30069	30070
240204	30069	233	0	0	30054	97	26	160142	125	80129	80012	125	80019	80019	650	416480	981487	0	0	30048	30069	30069	6	14	160163	200	80019	80019	200	80019	160038	30069	30068	1	1	160201	100	99	100	100	160000	100	0	0	80002	1	0	0	1	1	1	10118	0	16	0	0	0	30066	25	80000	160000	100	30069	30069	30080	30070	30069
240204	30069	233	0	0	30054	0	27	160143	125	80005	80013	125	80019	80019	650	416480	981487	0	0	30048	30069	30069	7	14	160163	200	80019	80019	200	80019	160038	30068	30068	1	1	160201	100	99	100	100	160000	100	0	0	80002	1	0	0	1	1	1	10119	2	16	0	0	0	30066	25	80000	160000	100	30070	30070	30088	30069	30070
240204	30068	233	0	0	30054	0	26	160143	125	80005	80013	125	80019	80019	650	416480	981487	0	0	30048	30068	30069	7	14	160163	200	80019	80019	200	80019	160038	30069	30068	1	1	160201	100	99	100	100	160000	100	0	0	80002	0	0	0	1	1	1	10118	0	16	0	0	0	30065	25	80000	160000	100	30070	30103	30070	30069	30069

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3756

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240024	30046	225	0	0	0	30030	0	26	160013	13	80000	80000	13	80000	80000	68	402642	963137	0	1	30026	30045	30045	0	3	24	160013	20	80000	80000	20	80000	160000	30045	30045	1	1	160021	10	9	10	10	160000	10	0	80000	0	0	10024	6	5	2	1	25	17	3	2	2	27	23	30042	3	31	80000	160000	10	30046	30046	30210	30046	30046
240024	30045	225	1	0	1	30030	0	26	161052	13	80000	80000	13	80000	80000	68	405696	963201	0	1	30026	30045	30045	0	3	24	160013	20	80000	80000	20	80000	160000	30045	30045	1	1	160021	10	9	10	10	160000	10	0	80000	8	0	10026	6	5	2	1	22	17	3	2	2	29	25	30042	3	31	80000	160000	10	30046	30046	30167	30046	30046
240024	30045	225	1	0	1	30030	0	26	160013	13	80000	80000	13	80000	80000	68	401606	960901	0	1	30026	30045	30045	0	3	24	160013	20	80000	80000	20	80000	160000	30045	30045	1	1	160021	10	9	10	10	160000	10	0	80000	35	3	10025	6	5	2	0	23	17	3	2	2	28	21	30042	3	31	80000	160000	10	30045	30046	30165	30046	30046
240024	30045	225	1	0	0	30030	0	26	160013	13	80000	80000	13	80000	80000	68	401606	960901	0	1	30026	30045	30045	0	3	49	160013	20	80000	80000	20	80000	160000	30045	30045	1	1	160021	10	9	10	10	160000	10	0	80000	2	0	10026	6	5	2	1	30	17	3	2	2	31	29	30042	3	31	80000	160000	10	30046	30046	30153	30048	30046
240024	30045	225	1	48	0	30030	0	26	160012	12	80000	80000	12	80000	80000	62	402075	961779	1	1	30026	30045	30045	0	3	24	160012	20	80000	80000	20	80000	160000	30045	30045	1	1	160021	10	9	10	10	160000	10	0	80000	0	0	10027	6	5	2	1	30	17	3	2	2	22	30	30045	2	41	80000	160000	10	30049	30183	30049	30050	30046
240024	30045	238	0	0	0	30030	92	26	160012	12	80000	80000	12	80000	80000	62	402075	961779	0	1	30029	30048	30048	0	3	24	160012	20	80000	80000	20	80000	160000	30048	30048	1	1	160021	10	9	10	10	160000	10	0	80000	5	0	10027	6	5	2	1	30	17	3	2	2	24	26	30045	2	41	80000	160000	10	30049	30164	30049	30049	30049
240024	30048	225	1	0	1	30033	0	61	160272	13	80000	80000	12	80000	80000	62	405220	961779	0	1	30029	30048	30048	0	3	24	160012	20	80000	80000	20	80000	160000	30048	30048	1	1	160021	10	9	10	10	160000	10	0	80000	2	3	10027	6	5	2	1	19	17	3	2	2	29	24	30045	2	41	80000	160000	10	30049	30151	30047	30049	30049
240024	30048	225	1	0	0	30033	0	26	160012	12	80000	80000	12	80000	80000	62	402075	961779	0	1	30029	30048	30048	0	3	24	160012	20	80000	80000	20	80000	160000	30048	30048	1	1	160021	10	9	10	10	160000	10	0	80000	1	0	10026	6	2	2	0	23	17	3	2	2	28	24	30045	2	41	80000	160000	10	30049	30142	30049	30049	30049
240024	30048	225	1	0	1	30033	0	26	160012	12	80000	80000	12	80000	80000	62	402075	961779	0	1	30029	30048	30048	0	3	24	160012	20	80000	80000	20	80000	160000	30048	30048	1	1	160021	10	9	10	10	160000	10	0	80000	1	0	10026	6	2	2	0	22	17	3	2	2	29	24	30045	2	41	80000	160000	10	30049	30114	30046	30049	30049
240024	30048	224	1	0	1	30033	0	26	160012	12	80000	80000	12	80000	80000	62	402075	961779	0	1	30029	30048	30048	0	3	24	160012	20	80000	80000	20	80000	160000	30048	30048	1	1	160021	10	9	10	10	160000	10	0	80000	1	0	10026	6	2	2	0	29	17	3	2	2	30	30	30045	2	41	80000	160000	10	30049	30116	30049	30052	30184

INS (general, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations