Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
ld1r { v0.2d }, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 1 mov x1, 2 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 2.000
Issues: 2.003
Integer unit issues: 0.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 1.003
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 22 | 24 | 3a | 3f | 46 | 49 | 51 | schedule uop (52) | schedule simd uop (54) | schedule ldst uop (55) | dispatch simd uop (57) | dispatch ldst uop (58) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5f | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd load (98) | inst ldst (9b) | 9d | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | f5 | f6 | f7 | f8 | fd |
62005 | 29406 | 221 | 0 | 19 | 0 | 0 | 17 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 4621 | 28769 | 1 | 1 | 17196 | 2003 | 1003 | 1000 | 1000 | 1000 | 5000 | 11933 | 5 | 22614 | 29052 | 29260 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 1000 | 29073 | 29063 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1001 | 3 | 3 | 1002 | 0 | 2 | 4 | 1000 | 1 | 1 | 3 | 0 | 0 | 12988 | 9242 | 6842 | 3060 | 5 | 44 | 20605 | 3147 | 3817 | 13 | 41 | 42 | 28382 | 16194 | 13863 | 15121 | 1000 | 1000 | 29272 | 29240 | 29236 | 29264 | 29271 |
62004 | 29246 | 220 | 1 | 14 | 1 | 1 | 11 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 4664 | 28784 | 0 | 0 | 17172 | 2004 | 1004 | 1000 | 1000 | 1000 | 5000 | 11951 | 0 | 22594 | 29011 | 29270 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 1000 | 29136 | 29119 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1001 | 3 | 3 | 1002 | 1 | 1 | 7 | 1000 | 3 | 1 | 2 | 1 | 0 | 12848 | 9186 | 6862 | 3076 | 13 | 40 | 20630 | 3088 | 3818 | 6 | 37 | 41 | 28338 | 16199 | 13913 | 15077 | 1000 | 1000 | 29172 | 29234 | 29253 | 29268 | 29252 |
62004 | 29215 | 218 | 1 | 15 | 1 | 1 | 17 | 1 | 0 | 0 | 0 | 0 | 5 | 1 | 0 | 4559 | 28738 | 0 | 0 | 17243 | 2004 | 1006 | 1000 | 1000 | 1000 | 5000 | 11943 | 2 | 22608 | 29066 | 29217 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 1000 | 29198 | 29127 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1001 | 2 | 2 | 1003 | 20 | 2 | 28 | 1000 | 3 | 1 | 3 | 1 | 1 | 12910 | 9255 | 6915 | 3104 | 6 | 45 | 20575 | 3143 | 3817 | 8 | 45 | 45 | 28337 | 16286 | 13942 | 14808 | 1000 | 1000 | 29302 | 29212 | 29271 | 29199 | 29269 |
62004 | 29274 | 219 | 1 | 16 | 1 | 1 | 17 | 1 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 4616 | 28752 | 0 | 0 | 17308 | 2004 | 1004 | 1000 | 1000 | 1000 | 5000 | 11949 | 3 | 22625 | 28995 | 29288 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 1001 | 29104 | 29137 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1001 | 1 | 2 | 1002 | 17 | 1 | 10 | 1000 | 3 | 1 | 3 | 1 | 1 | 12996 | 9116 | 6833 | 3109 | 6 | 45 | 20615 | 3062 | 3812 | 11 | 38 | 42 | 28387 | 16309 | 13741 | 15072 | 1000 | 1000 | 29352 | 29246 | 29209 | 29271 | 29255 |
62004 | 29249 | 219 | 1 | 17 | 1 | 1 | 19 | 1 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 4622 | 28801 | 0 | 0 | 17258 | 2003 | 1004 | 1000 | 1000 | 1000 | 5000 | 11937 | 1 | 22595 | 29099 | 29221 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 1000 | 29090 | 29097 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1001 | 3 | 3 | 1002 | 1 | 1 | 1 | 1000 | 3 | 1 | 3 | 1 | 1 | 12972 | 9210 | 6870 | 3096 | 6 | 40 | 20570 | 3124 | 3819 | 4 | 42 | 42 | 28352 | 16389 | 13945 | 14980 | 1000 | 1000 | 29330 | 29195 | 29311 | 29286 | 29200 |
62004 | 29167 | 219 | 1 | 15 | 1 | 1 | 16 | 1 | 0 | 0 | 0 | 0 | 16 | 1 | 0 | 4619 | 28729 | 0 | 0 | 17284 | 2003 | 1004 | 1000 | 1000 | 1000 | 5000 | 11952 | 4 | 22644 | 28992 | 29138 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 1000 | 29146 | 29115 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1001 | 4 | 2 | 1003 | 0 | 0 | 1 | 1000 | 3 | 1 | 2 | 1 | 2 | 12892 | 9154 | 6837 | 3060 | 5 | 41 | 20599 | 3074 | 3818 | 9 | 39 | 44 | 28320 | 16285 | 13745 | 15043 | 1000 | 1000 | 28969 | 29280 | 29279 | 29210 | 29248 |
62004 | 29185 | 218 | 1 | 18 | 1 | 0 | 16 | 1 | 0 | 0 | 0 | 0 | 5 | 1 | 0 | 4652 | 28721 | 0 | 0 | 17127 | 2003 | 1004 | 1000 | 1000 | 1000 | 5000 | 11942 | 3 | 22609 | 29059 | 29239 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 1000 | 29058 | 29069 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1001 | 10 | 3 | 1001 | 28 | 1 | 7 | 1000 | 2 | 1 | 2 | 1 | 1 | 13077 | 9196 | 6820 | 3066 | 5 | 43 | 20627 | 3103 | 3815 | 5 | 42 | 44 | 28372 | 16100 | 13763 | 15050 | 1000 | 1000 | 29269 | 29184 | 29353 | 29217 | 29299 |
62004 | 29191 | 219 | 1 | 18 | 1 | 1 | 11 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 4675 | 28839 | 0 | 0 | 17225 | 2004 | 1004 | 1000 | 1000 | 1000 | 5000 | 11948 | 5 | 22708 | 29019 | 29176 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 1000 | 29153 | 29075 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1001 | 4 | 4 | 1002 | 23 | 0 | 1297 | 1000 | 2 | 1 | 3 | 1 | 1 | 12947 | 9221 | 7014 | 3082 | 5 | 42 | 20590 | 3086 | 3817 | 11 | 44 | 40 | 28337 | 16215 | 13862 | 15162 | 1000 | 1000 | 29398 | 29176 | 29255 | 29267 | 29218 |
62004 | 29238 | 219 | 1 | 12 | 0 | 0 | 12 | 1 | 1 | 1 | 0 | 0 | 44 | 1 | 0 | 4592 | 28724 | 0 | 0 | 17246 | 2002 | 1003 | 1000 | 1000 | 1000 | 5000 | 11926 | 0 | 22646 | 29035 | 29220 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 1000 | 29132 | 29131 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1001 | 3 | 2 | 1000 | 73 | 0 | 4 | 1000 | 2 | 1 | 3 | 0 | 0 | 12835 | 9136 | 6864 | 3052 | 8 | 40 | 20618 | 3081 | 3816 | 12 | 45 | 44 | 28308 | 16374 | 13785 | 14836 | 1000 | 1000 | 29195 | 29274 | 29244 | 29250 | 29198 |
62004 | 29290 | 219 | 0 | 18 | 0 | 0 | 14 | 0 | 1 | 0 | 0 | 0 | 3 | 1 | 0 | 4581 | 28781 | 1 | 1 | 17231 | 2003 | 1003 | 1000 | 1000 | 1000 | 5000 | 12027 | 1 | 22632 | 29049 | 29277 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 1000 | 29113 | 29153 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1001 | 1 | 3 | 1001 | 5 | 0 | 63 | 1000 | 2 | 0 | 2 | 0 | 0 | 12906 | 9374 | 6869 | 3066 | 8 | 45 | 20616 | 3072 | 3813 | 13 | 44 | 45 | 28375 | 16246 | 13788 | 14911 | 1000 | 1000 | 29269 | 29326 | 29282 | 29280 | 29233 |
Chain cycles: 3
Code:
ld1r { v0.2d }, [x6] fmov x0, d0 eor x8, x8, x0 eor x8, x8, x0 add x6, x6, x8
mov x0, 1 mov x1, 2 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 3 chain cycles): 11.0054
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 1f | 22 | 23 | 24 | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6b | 6d | 6e | map stall dispatch (70) | int prf full (71) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | b5 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | cd | cf | d0 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
60205 | 140057 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 140020 | 139406 | 129347 | 25 | 70100 | 40100 | 20000 | 10000 | 30100 | 20000 | 10000 | 1264020 | 6692947 | 14310939 | 0 | 140011 | 0 | 140054 | 140035 | 131800 | 0 | 3 | 132389 | 60100 | 30200 | 10000 | 20000 | 60200 | 10213 | 20000 | 140051 | 140051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 3210 | 0 | 2 | 139 | 6 | 1 | 139568 | 40000 | 13 | 0 | 10 | 10000 | 10000 | 40100 | 140055 | 140036 | 140036 | 140055 | 140055 |
60204 | 140035 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 140039 | 139427 | 129347 | 25 | 70102 | 40100 | 20002 | 10000 | 30100 | 20000 | 10000 | 1263803 | 6693878 | 14310939 | 0 | 140011 | 3 | 140035 | 140054 | 131800 | 0 | 3 | 132399 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 20000 | 140431 | 140051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 0 | 10000 | 1 | 0 | 0 | 0 | 0 | 0 | 3210 | 0 | 1 | 127 | 1 | 1 | 139565 | 40000 | 13 | 13 | 13 | 10000 | 10000 | 40100 | 140055 | 140055 | 140036 | 140055 | 140055 |
60204 | 140054 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 140039 | 139406 | 129365 | 25 | 70100 | 40100 | 20002 | 10000 | 30100 | 20000 | 10000 | 1264020 | 6693235 | 14318556 | 0 | 140030 | 0 | 140284 | 140057 | 131793 | 0 | 3 | 132389 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 20000 | 140054 | 140035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10001 | 0 | 0 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 3210 | 0 | 1 | 139 | 1 | 1 | 139565 | 40000 | 0 | 13 | 13 | 10000 | 10000 | 40100 | 140055 | 140055 | 140055 | 140036 | 140036 |
60204 | 140035 | 1049 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 140039 | 139427 | 129365 | 25 | 70102 | 40100 | 20000 | 10000 | 30100 | 20000 | 10000 | 1263803 | 6692947 | 14312282 | 0 | 140030 | 0 | 140035 | 140035 | 131797 | 0 | 3 | 132399 | 60100 | 30200 | 10000 | 20000 | 60200 | 10211 | 20000 | 140054 | 140035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 3210 | 0 | 1 | 139 | 1 | 1 | 139565 | 40000 | 13 | 0 | 13 | 10000 | 10000 | 40100 | 140036 | 140055 | 140055 | 140103 | 140055 |
60204 | 140054 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 140020 | 139406 | 129363 | 25 | 70102 | 40100 | 20002 | 10000 | 30100 | 20000 | 10000 | 1264020 | 6693878 | 14310939 | 1 | 140011 | 0 | 140051 | 140035 | 131800 | 0 | 3 | 132382 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 20000 | 140054 | 140035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 3210 | 0 | 1 | 139 | 1 | 1 | 139559 | 40000 | 0 | 0 | 10 | 10000 | 10000 | 40100 | 140055 | 140057 | 140060 | 140432 | 140055 |
60204 | 140054 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 140039 | 139411 | 129363 | 25 | 70100 | 40100 | 20002 | 10000 | 30100 | 20000 | 10000 | 1264020 | 6693734 | 14312282 | 0 | 140030 | 0 | 140037 | 140054 | 131793 | 0 | 3 | 132382 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 20000 | 140054 | 140051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 2 | 3 | 0 | 48 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 3210 | 0 | 1 | 139 | 1 | 1 | 139565 | 40000 | 0 | 0 | 13 | 10000 | 10000 | 40100 | 140055 | 140036 | 140055 | 140055 | 140055 |
60204 | 140054 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 140036 | 139427 | 129347 | 25 | 70102 | 40100 | 20000 | 10000 | 30100 | 20000 | 10000 | 1263958 | 6692947 | 14312282 | 1 | 140030 | 0 | 140054 | 140054 | 131800 | 0 | 3 | 132399 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 20000 | 140035 | 140035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 0 | 10000 | 0 | 0 | 1 | 0 | 0 | 0 | 3210 | 0 | 1 | 139 | 1 | 1 | 139565 | 40000 | 13 | 13 | 0 | 10000 | 10000 | 40100 | 140052 | 140052 | 140428 | 140055 | 140058 |
60204 | 140035 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 40 | 352 | 0 | 0 | 0 | 140039 | 139427 | 129365 | 25 | 70102 | 40100 | 20002 | 10000 | 30100 | 20000 | 10000 | 1263803 | 6693878 | 14308701 | 0 | 140030 | 0 | 140051 | 140051 | 131797 | 0 | 3 | 132399 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 20000 | 140035 | 140051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 0 | 10000 | 0 | 3 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 3210 | 0 | 1 | 127 | 1 | 1 | 139559 | 40000 | 10 | 13 | 10 | 10000 | 10000 | 40100 | 140055 | 140055 | 140036 | 140052 | 140055 |
60204 | 140054 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 140039 | 139427 | 129365 | 25 | 70102 | 40100 | 20002 | 10000 | 30100 | 20000 | 10000 | 1263803 | 6693878 | 14308701 | 0 | 140011 | 0 | 140054 | 140035 | 131800 | 0 | 3 | 132382 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 20000 | 140054 | 140051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 0 | 10000 | 0 | 0 | 1 | 0 | 0 | 0 | 3210 | 0 | 1 | 139 | 1 | 1 | 139565 | 40000 | 13 | 0 | 0 | 10000 | 10000 | 40100 | 140055 | 140055 | 140055 | 140036 | 140055 |
60204 | 140054 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 82 | 0 | 1 | 0 | 0 | 140039 | 139427 | 129365 | 25 | 70102 | 40100 | 20000 | 10000 | 30100 | 20000 | 10000 | 1263803 | 6693734 | 14308701 | 0 | 140030 | 0 | 140035 | 140060 | 131800 | 0 | 3 | 132605 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 20000 | 140055 | 140423 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 3210 | 0 | 1 | 139 | 1 | 1 | 139546 | 40000 | 0 | 0 | 10 | 10000 | 10000 | 40100 | 140055 | 140036 | 140055 | 140052 | 140055 |
Result (median cycles for code, minus 3 chain cycles): 11.0050
retire uop (01) | cycle (02) | 03 | 09 | l2 tlb miss data (0b) | 0e | 0f | 18 | 1e | 22 | 23 | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | int prf full (71) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | ac | af | b5 | l1d cache miss ld nonspec (bf) | branch cond mispred nonspec (c5) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
60025 | 140047 | 1048 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 140020 | 139394 | 129359 | 25 | 70010 | 40010 | 20002 | 10000 | 30010 | 20000 | 10000 | 1264443 | 6693538 | 14325933 | 1 | 140013 | 140052 | 140050 | 131818 | 0 | 3 | 132433 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 20000 | 140047 | 140035 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 5 | 0 | 10000 | 1 | 1 | 0 | 0 | 3140 | 3 | 111 | 3 | 3 | 139554 | 40000 | 9 | 6 | 0 | 10000 | 10000 | 40010 | 140051 | 140036 | 140048 | 140036 | 140051 |
60024 | 140047 | 1049 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 140032 | 139397 | 129362 | 25 | 70010 | 40010 | 20002 | 10000 | 30010 | 20000 | 10000 | 1264443 | 6693522 | 14325829 | 0 | 140026 | 140050 | 140035 | 131803 | 0 | 3 | 132435 | 60010 | 30020 | 10062 | 20000 | 60020 | 10000 | 20000 | 140050 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 10000 | 1 | 0 | 10000 | 1 | 0 | 0 | 0 | 3140 | 3 | 113 | 3 | 3 | 139566 | 40000 | 9 | 6 | 9 | 10000 | 10000 | 40010 | 140051 | 140036 | 140067 | 140036 | 140048 |
60024 | 140035 | 1048 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 140035 | 139397 | 129347 | 25 | 70012 | 40010 | 20000 | 10000 | 30010 | 20000 | 10000 | 1264477 | 6693685 | 14325829 | 0 | 140026 | 140050 | 140047 | 131815 | 0 | 3 | 132506 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 20000 | 140050 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 10000 | 0 | 0 | 10000 | 0 | 1 | 0 | 0 | 3140 | 3 | 113 | 3 | 3 | 139569 | 40000 | 6 | 6 | 9 | 10000 | 10000 | 40010 | 140036 | 140036 | 140036 | 140051 | 140036 |
60024 | 140035 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 140035 | 139397 | 129362 | 25 | 70012 | 40010 | 20002 | 10000 | 30010 | 20000 | 10000 | 1264477 | 6692947 | 14325829 | 0 | 140011 | 140050 | 140050 | 131803 | 0 | 3 | 132436 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 20000 | 140035 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3140 | 3 | 111 | 3 | 3 | 139566 | 40000 | 9 | 9 | 9 | 10000 | 10000 | 40010 | 140048 | 140051 | 140050 | 140049 | 140037 |
60024 | 140108 | 1049 | 0 | 1 | 0 | 0 | 0 | 18 | 1 | 0 | 140035 | 139405 | 129362 | 25 | 70035 | 40010 | 20002 | 10000 | 30010 | 20000 | 10000 | 1264477 | 6693685 | 14325829 | 0 | 140031 | 140050 | 140035 | 131818 | 0 | 3 | 132438 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 20000 | 140050 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3140 | 3 | 113 | 3 | 3 | 139569 | 40000 | 6 | 6 | 9 | 10000 | 10000 | 40010 | 140052 | 140038 | 140053 | 140423 | 140036 |
60024 | 140050 | 1049 | 0 | 0 | 0 | 0 | 0 | 6 | 1 | 0 | 140032 | 139394 | 129362 | 25 | 70010 | 40010 | 20002 | 10000 | 30010 | 20000 | 10000 | 1264477 | 6693685 | 14325829 | 1 | 140026 | 140035 | 140035 | 131803 | 0 | 3 | 132433 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 20000 | 140047 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3140 | 2 | 111 | 2 | 3 | 139566 | 40000 | 9 | 6 | 9 | 10000 | 10000 | 40010 | 140051 | 140036 | 140036 | 140051 | 140051 |
60024 | 140050 | 1049 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 140020 | 139397 | 129362 | 25 | 70012 | 40010 | 20002 | 10000 | 30010 | 20000 | 10000 | 1264477 | 6693685 | 14321442 | 0 | 140026 | 140082 | 140050 | 131803 | 0 | 3 | 132478 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 20000 | 140050 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 0 | 0 | 3140 | 3 | 113 | 3 | 2 | 139554 | 40000 | 0 | 0 | 6 | 10000 | 10000 | 40010 | 140036 | 140051 | 140051 | 140036 | 140051 |
60024 | 140050 | 1049 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 140079 | 139394 | 129362 | 25 | 70010 | 40010 | 20002 | 10000 | 30010 | 20000 | 10000 | 1264429 | 6693685 | 14321442 | 0 | 140011 | 140035 | 140050 | 131803 | 0 | 3 | 132462 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 20000 | 140035 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3177 | 3 | 111 | 3 | 3 | 139569 | 40000 | 9 | 6 | 0 | 10000 | 10000 | 40010 | 140048 | 140048 | 140048 | 140036 | 140048 |
60024 | 140050 | 1049 | 0 | 0 | 0 | 0 | 0 | 6 | 1 | 0 | 140040 | 139397 | 129362 | 25 | 70010 | 40010 | 20002 | 10000 | 30010 | 20000 | 10000 | 1264477 | 6693685 | 14325829 | 1 | 140026 | 140050 | 140050 | 131818 | 0 | 3 | 132466 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 20000 | 140035 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3140 | 2 | 113 | 3 | 3 | 139568 | 40000 | 0 | 9 | 9 | 10000 | 10000 | 40010 | 140051 | 140051 | 140036 | 140082 | 140048 |
60024 | 140035 | 1049 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 140035 | 139394 | 129362 | 25 | 70012 | 40010 | 20000 | 10000 | 30010 | 20000 | 10000 | 1264477 | 6693685 | 14326555 | 1 | 140011 | 140055 | 140035 | 131818 | 0 | 3 | 132478 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 20000 | 140050 | 140035 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 1 | 10 | 10000 | 1 | 10000 | 1 | 0 | 10000 | 0 | 1 | 0 | 0 | 3140 | 3 | 111 | 3 | 2 | 139569 | 40000 | 0 | 0 | 9 | 10000 | 10000 | 40010 | 140051 | 140051 | 140051 | 140048 | 140036 |
Count: 8
Code:
ld1r { v0.2d }, [x6] ld1r { v0.2d }, [x6] ld1r { v0.2d }, [x6] ld1r { v0.2d }, [x6] ld1r { v0.2d }, [x6] ld1r { v0.2d }, [x6] ld1r { v0.2d }, [x6] ld1r { v0.2d }, [x6]
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.3342
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 0e | 0f | 1e | 22 | 23 | 3a | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160205 | 26737 | 200 | 1 | 0 | 1 | 1 | 0 | 102 | 0 | 0 | 3 | 26722 | 2 | 0 | 7 | 0 | 25 | 160165 | 100 | 80019 | 80000 | 100 | 80000 | 80000 | 500 | 1176870 | 1878294 | 1 | 26697 | 26737 | 26715 | 6659 | 3 | 6695 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 80000 | 26737 | 26737 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80019 | 19 | 43 | 80019 | 1 | 0 | 2 | 21 | 80039 | 6 | 1 | 0 | 44 | 0 | 0 | 0 | 5110 | 3 | 16 | 3 | 3 | 26729 | 14 | 10 | 0 | 80000 | 80000 | 100 | 26733 | 26709 | 26733 | 26709 | 26741 |
160204 | 26708 | 200 | 0 | 0 | 0 | 0 | 1 | 45 | 1 | 0 | 0 | 26713 | 0 | 0 | 0 | 19 | 25 | 160144 | 100 | 80044 | 80000 | 100 | 80000 | 80000 | 500 | 1168880 | 1884011 | 1 | 26713 | 26732 | 26708 | 6630 | 3 | 6690 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 80000 | 26708 | 26728 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 43 | 80039 | 0 | 2 | 0 | 54 | 80000 | 6 | 1 | 39 | 44 | 0 | 0 | 0 | 5110 | 3 | 16 | 2 | 3 | 26725 | 14 | 0 | 3 | 80000 | 80000 | 100 | 26733 | 26729 | 26736 | 26733 | 26733 |
160204 | 26728 | 200 | 0 | 0 | 0 | 1 | 1 | 44 | 0 | 0 | 0 | 26717 | 2 | 0 | 0 | 19 | 25 | 160144 | 100 | 80044 | 80000 | 100 | 80000 | 80000 | 500 | 1169623 | 1880202 | 1 | 26715 | 26720 | 26732 | 6630 | 3 | 6666 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 80000 | 26732 | 26728 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 43 | 80000 | 0 | 0 | 0 | 39 | 80000 | 6 | 1 | 39 | 0 | 0 | 0 | 0 | 5110 | 3 | 16 | 3 | 3 | 26705 | 14 | 0 | 0 | 80000 | 80000 | 100 | 26733 | 26733 | 26733 | 26733 | 26709 |
160204 | 26728 | 200 | 0 | 0 | 0 | 1 | 1 | 44 | 0 | 0 | 0 | 26717 | 0 | 12 | 0 | 19 | 25 | 160100 | 100 | 80000 | 80000 | 100 | 80000 | 80000 | 500 | 1174628 | 1887067 | 1 | 26713 | 26732 | 26732 | 6654 | 3 | 6690 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 80000 | 26732 | 26728 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 0 | 80000 | 0 | 0 | 0 | 0 | 80000 | 0 | 1 | 0 | 43 | 0 | 0 | 0 | 5110 | 3 | 16 | 2 | 3 | 26729 | 0 | 14 | 3 | 80000 | 80000 | 100 | 26709 | 26709 | 26733 | 26733 | 26733 |
160204 | 26728 | 200 | 0 | 0 | 0 | 1 | 0 | 23 | 0 | 0 | 3 | 26700 | 3 | 7 | 0 | 19 | 25 | 160165 | 100 | 80064 | 80000 | 100 | 80000 | 80000 | 500 | 1169295 | 1883532 | 1 | 26726 | 26737 | 26737 | 6659 | 3 | 6695 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 80000 | 26737 | 26737 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80019 | 19 | 43 | 80058 | 0 | 0 | 0 | 60 | 80000 | 6 | 0 | 58 | 0 | 19 | 2 | 0 | 5110 | 3 | 16 | 3 | 3 | 26734 | 0 | 13 | 0 | 80000 | 80000 | 100 | 26738 | 26716 | 26738 | 26716 | 26716 |
160204 | 26715 | 200 | 1 | 1 | 0 | 1 | 0 | 44 | 0 | 0 | 1 | 26717 | 2 | 12 | 0 | 0 | 25 | 160144 | 100 | 80000 | 80000 | 100 | 80000 | 80000 | 500 | 1168880 | 1887334 | 1 | 26712 | 26708 | 26708 | 6650 | 3 | 6666 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 80000 | 26708 | 26728 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 0 | 80038 | 0 | 0 | 0 | 38 | 80038 | 6 | 1 | 0 | 43 | 0 | 0 | 0 | 5110 | 3 | 16 | 3 | 3 | 26705 | 14 | 14 | 3 | 80000 | 80000 | 100 | 26733 | 26709 | 26729 | 26733 | 26709 |
160204 | 26728 | 200 | 0 | 0 | 0 | 1 | 0 | 44 | 0 | 0 | 1 | 26693 | 2 | 0 | 1 | 19 | 25 | 160144 | 100 | 80000 | 80000 | 100 | 80000 | 80000 | 500 | 1169085 | 1885214 | 1 | 26718 | 26732 | 26708 | 6630 | 3 | 6690 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 80000 | 26708 | 26728 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 44 | 80039 | 0 | 0 | 0 | 38 | 80038 | 6 | 0 | 0 | 44 | 0 | 0 | 0 | 5110 | 3 | 16 | 3 | 3 | 26705 | 0 | 0 | 3 | 80000 | 80000 | 100 | 26709 | 26733 | 26729 | 26733 | 26733 |
160204 | 26708 | 201 | 0 | 0 | 0 | 1 | 1 | 44 | 0 | 0 | 1 | 26717 | 0 | 12 | 1 | 0 | 25 | 160144 | 100 | 80044 | 80000 | 100 | 80000 | 80000 | 500 | 1168880 | 1883573 | 1 | 26713 | 26732 | 26732 | 6650 | 3 | 6666 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 80000 | 26708 | 26728 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 43 | 80038 | 0 | 0 | 0 | 43 | 80038 | 0 | 1 | 0 | 44 | 0 | 0 | 0 | 5112 | 3 | 16 | 3 | 3 | 26705 | 14 | 10 | 0 | 80000 | 80000 | 100 | 26709 | 26733 | 26733 | 26709 | 26709 |
160204 | 26732 | 200 | 0 | 0 | 0 | 1 | 0 | 44 | 1 | 0 | 1 | 26693 | 0 | 1 | 1 | 19 | 25 | 160144 | 100 | 80000 | 80000 | 100 | 80000 | 80000 | 500 | 1174887 | 1887228 | 1 | 26727 | 26737 | 26737 | 6637 | 3 | 6673 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 80000 | 26715 | 26737 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80019 | 20 | 0 | 80061 | 1 | 0 | 1 | 21 | 80000 | 6 | 0 | 58 | 43 | 19 | 0 | 0 | 5110 | 3 | 16 | 2 | 3 | 26712 | 13 | 0 | 2 | 80000 | 80000 | 100 | 26716 | 26716 | 26738 | 26738 | 26738 |
160204 | 26737 | 200 | 1 | 1 | 1 | 1 | 1 | 67 | 0 | 0 | 0 | 26700 | 2 | 0 | 7 | 0 | 25 | 160165 | 100 | 80019 | 80000 | 100 | 80000 | 80000 | 500 | 1170179 | 1887160 | 1 | 26722 | 26728 | 26708 | 6630 | 3 | 6666 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 80000 | 26732 | 26728 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 43 | 80038 | 0 | 0 | 0 | 38 | 80038 | 0 | 1 | 0 | 43 | 0 | 0 | 0 | 5110 | 3 | 16 | 3 | 3 | 26729 | 14 | 14 | 0 | 80000 | 80000 | 100 | 26729 | 26709 | 26733 | 26709 | 26709 |
Result (median cycles for code divided by count): 0.3340
retire uop (01) | cycle (02) | 03 | l1i tlb fill (04) | 09 | l2 tlb miss data (0b) | 0e | 0f | 1e | 1f | 22 | 23 | 3a | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | simd prf full (72) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | a5 | ld unit uop (a6) | l1d cache writeback (a8) | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | c2 | branch cond mispred nonspec (c5) | cf | d2 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ea | eb | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160025 | 26725 | 200 | 1 | 1 | 0 | 1 | 1 | 41 | 0 | 1 | 0 | 1 | 26708 | 0 | 18 | 18 | 12 | 25 | 160052 | 10 | 80041 | 80000 | 10 | 80000 | 80000 | 50 | 1170107 | 1884807 | 0 | 26706 | 26729 | 26723 | 6668 | 0 | 3 | 6703 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 80000 | 26723 | 26723 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 39 | 0 | 80000 | 0 | 35 | 80035 | 6 | 1 | 35 | 39 | 0 | 0 | 5020 | 0 | 3 | 16 | 5 | 5 | 26720 | 0 | 6 | 80000 | 80000 | 10 | 26724 | 26709 | 26724 | 26724 | 26724 |
160024 | 26723 | 200 | 0 | 0 | 0 | 1 | 1 | 41 | 0 | 1 | 0 | 1 | 26708 | 2 | 18 | 18 | 12 | 25 | 160051 | 10 | 80041 | 80000 | 10 | 80000 | 80000 | 50 | 1170107 | 1884807 | 0 | 26704 | 26708 | 26723 | 6653 | 0 | 3 | 6703 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 80000 | 26708 | 26723 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 39 | 0 | 80035 | 0 | 35 | 80035 | 6 | 1 | 35 | 39 | 0 | 0 | 5020 | 0 | 2 | 16 | 3 | 5 | 26705 | 6 | 0 | 80000 | 80000 | 10 | 26724 | 26724 | 26724 | 26724 | 26724 |
160024 | 26708 | 200 | 0 | 0 | 0 | 1 | 0 | 41 | 0 | 0 | 0 | 1 | 26708 | 2 | 18 | 18 | 11 | 25 | 160051 | 10 | 80000 | 80000 | 10 | 80000 | 80000 | 50 | 1170107 | 1884807 | 0 | 26711 | 26723 | 26723 | 6653 | 0 | 3 | 6703 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 80000 | 26723 | 26708 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 39 | 0 | 80035 | 1 | 35 | 80035 | 6 | 1 | 35 | 0 | 0 | 0 | 5020 | 0 | 2 | 16 | 2 | 3 | 26720 | 6 | 0 | 80000 | 80000 | 10 | 26724 | 26724 | 26724 | 26724 | 26724 |
160024 | 26723 | 200 | 0 | 0 | 0 | 1 | 1 | 41 | 0 | 1 | 0 | 1 | 26693 | 2 | 18 | 18 | 12 | 25 | 160051 | 10 | 80041 | 80000 | 10 | 80000 | 80000 | 50 | 1169844 | 1884807 | 0 | 26715 | 26729 | 26708 | 6668 | 0 | 3 | 6703 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 80000 | 26723 | 27130 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 0 | 0 | 80000 | 0 | 35 | 80035 | 0 | 1 | 0 | 0 | 0 | 0 | 5020 | 0 | 5 | 16 | 5 | 5 | 26720 | 6 | 6 | 80000 | 80000 | 10 | 26724 | 26709 | 26724 | 26724 | 26709 |
160024 | 26708 | 200 | 0 | 0 | 0 | 1 | 0 | 41 | 0 | 1 | 0 | 0 | 26708 | 2 | 18 | 18 | 12 | 25 | 160051 | 10 | 80000 | 80000 | 10 | 80000 | 80000 | 50 | 1168880 | 1884807 | 0 | 26704 | 26723 | 26708 | 6668 | 0 | 3 | 6688 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 80000 | 26708 | 26723 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 0 | 0 | 80035 | 0 | 35 | 80035 | 0 | 1 | 0 | 39 | 0 | 0 | 5020 | 0 | 3 | 16 | 5 | 6 | 26720 | 6 | 6 | 80000 | 80000 | 10 | 26709 | 26709 | 26724 | 26709 | 26709 |
160024 | 26723 | 200 | 0 | 0 | 0 | 1 | 0 | 41 | 0 | 1 | 0 | 1 | 26708 | 2 | 0 | 18 | 11 | 25 | 160051 | 10 | 80000 | 80000 | 10 | 80000 | 80000 | 50 | 1170107 | 1884807 | 0 | 26704 | 26723 | 26723 | 6653 | 0 | 3 | 6703 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 80000 | 26723 | 26708 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 39 | 0 | 80000 | 0 | 35 | 80035 | 6 | 1 | 35 | 39 | 0 | 0 | 5020 | 0 | 5 | 16 | 3 | 3 | 26720 | 0 | 0 | 80000 | 80000 | 10 | 26724 | 26724 | 26724 | 26724 | 26709 |
160024 | 26723 | 200 | 0 | 0 | 0 | 1 | 0 | 41 | 0 | 1 | 0 | 1 | 26708 | 0 | 18 | 0 | 12 | 25 | 160010 | 10 | 80000 | 80000 | 10 | 80000 | 80000 | 50 | 1168880 | 1884807 | 0 | 26712 | 26723 | 26723 | 6668 | 0 | 3 | 6703 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 80000 | 26708 | 26708 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 39 | 0 | 80035 | 0 | 35 | 80035 | 6 | 1 | 35 | 39 | 0 | 0 | 5020 | 0 | 3 | 16 | 3 | 2 | 26720 | 6 | 0 | 80000 | 80000 | 10 | 26724 | 26709 | 26709 | 26709 | 26724 |
160024 | 26723 | 200 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 26708 | 2 | 18 | 18 | 0 | 25 | 160051 | 10 | 80041 | 80000 | 10 | 80000 | 80000 | 50 | 1170107 | 1884807 | 0 | 26712 | 26723 | 26723 | 6653 | 0 | 3 | 6703 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 80000 | 26708 | 26723 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 39 | 0 | 80035 | 0 | 35 | 80000 | 6 | 1 | 0 | 0 | 0 | 0 | 5020 | 0 | 3 | 16 | 3 | 2 | 26705 | 0 | 6 | 80000 | 80000 | 10 | 26724 | 26724 | 26724 | 26724 | 26709 |
160024 | 26723 | 200 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 26708 | 2 | 0 | 18 | 3 | 25 | 160051 | 10 | 80041 | 80000 | 10 | 80000 | 80000 | 50 | 1170107 | 1884807 | 0 | 26712 | 26723 | 26723 | 6653 | 0 | 3 | 6703 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 80000 | 26723 | 26708 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 39 | 0 | 80035 | 0 | 35 | 80035 | 6 | 0 | 35 | 39 | 0 | 0 | 5020 | 0 | 6 | 16 | 5 | 5 | 26720 | 0 | 6 | 80000 | 80000 | 10 | 26724 | 26724 | 26724 | 26724 | 26724 |
160024 | 26708 | 200 | 0 | 0 | 0 | 1 | 0 | 41 | 0 | 1 | 0 | 1 | 26708 | 0 | 18 | 18 | 0 | 25 | 160052 | 10 | 80041 | 80000 | 10 | 80000 | 80000 | 50 | 1170107 | 1884807 | 1 | 26697 | 26723 | 26723 | 6668 | 0 | 3 | 6703 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 80000 | 26726 | 26723 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 39 | 0 | 80035 | 1 | 35 | 80035 | 0 | 1 | 0 | 39 | 0 | 0 | 5020 | 0 | 3 | 16 | 3 | 2 | 26720 | 6 | 0 | 80000 | 80000 | 10 | 26709 | 26709 | 26709 | 26712 | 26724 |