Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
ld1r { v0.8b }, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 1 mov x1, 2 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 2.000
Issues: 2.003
Integer unit issues: 0.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 1.003
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 0e | 0f | 1e | 22 | 24 | 3a | 3f | 43 | 46 | 49 | 51 | schedule uop (52) | schedule simd uop (54) | schedule ldst uop (55) | dispatch simd uop (57) | dispatch ldst uop (58) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5f | 60 | 61 | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd load (98) | inst ldst (9b) | 9d | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | f5 | f6 | f7 | f8 | fd |
62005 | 28561 | 213 | 1 | 15 | 1 | 0 | 15 | 1 | 0 | 0 | 48 | 1 | 0 | 5257 | 27939 | 0 | 0 | 1 | 16292 | 2001 | 1004 | 1000 | 1000 | 1000 | 5000 | 11938 | 2 | 0 | 0 | 22710 | 28306 | 28339 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 1000 | 28201 | 28210 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1003 | 1 | 3 | 1002 | 0 | 2 | 1 | 1000 | 1 | 3 | 1 | 0 | 0 | 13848 | 10165 | 7210 | 3452 | 9 | 55 | 19600 | 3366 | 3825 | 10 | 46 | 40 | 27904 | 14701 | 12450 | 13288 | 1000 | 1000 | 28091 | 28142 | 28165 | 28252 | 28307 |
62004 | 28300 | 212 | 0 | 15 | 0 | 0 | 16 | 0 | 0 | 0 | 386 | 1 | 0 | 5263 | 28023 | 1 | 1 | 1 | 16466 | 2000 | 1004 | 1000 | 1000 | 1000 | 5000 | 11924 | 5 | 0 | 0 | 22694 | 28041 | 28194 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 1000 | 28352 | 28082 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 0 | 2 | 1003 | 0 | 0 | 1 | 1003 | 0 | 1 | 3 | 0 | 0 | 13517 | 10084 | 7042 | 3397 | 12 | 37 | 19671 | 3240 | 3817 | 10 | 40 | 43 | 27959 | 13897 | 12790 | 13301 | 1000 | 1000 | 28211 | 28509 | 28424 | 28338 | 28066 |
62004 | 28390 | 213 | 0 | 12 | 0 | 0 | 17 | 1 | 0 | 0 | 303 | 1 | 0 | 4883 | 27970 | 1 | 1 | 0 | 16447 | 2002 | 1004 | 1000 | 1000 | 1000 | 5000 | 11948 | 3 | 0 | 0 | 22680 | 28073 | 28369 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 1000 | 28179 | 28085 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 0 | 3 | 1003 | 0 | 0 | 3 | 1003 | 1 | 3 | 2 | 0 | 0 | 13544 | 10112 | 7149 | 3450 | 8 | 38 | 19484 | 3339 | 3817 | 12 | 34 | 32 | 27813 | 14679 | 12251 | 13315 | 1000 | 1000 | 28128 | 28240 | 28323 | 28346 | 28236 |
62004 | 28257 | 212 | 0 | 13 | 0 | 0 | 15 | 0 | 0 | 0 | 15 | 1 | 0 | 5083 | 27988 | 1 | 1 | 1 | 16365 | 2004 | 1004 | 1000 | 1000 | 1000 | 5000 | 11949 | 7 | 0 | 0 | 22685 | 28092 | 28468 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 1000 | 28267 | 28175 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 0 | 0 | 1003 | 0 | 0 | 1 | 1001 | 0 | 1 | 2 | 0 | 0 | 13846 | 10285 | 7244 | 3341 | 9 | 36 | 19629 | 3399 | 3819 | 11 | 38 | 36 | 27901 | 13952 | 12533 | 13319 | 1000 | 1000 | 28190 | 28222 | 28196 | 28048 | 28434 |
62004 | 28402 | 211 | 0 | 17 | 0 | 0 | 19 | 0 | 0 | 0 | 31 | 1 | 0 | 5191 | 28033 | 1 | 1 | 1 | 16206 | 2002 | 1002 | 1000 | 1000 | 1000 | 5000 | 11940 | 7 | 0 | 0 | 22675 | 28131 | 28154 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 1000 | 28306 | 28352 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 0 | 3 | 1003 | 0 | 0 | 1 | 1003 | 1 | 1 | 3 | 0 | 0 | 13627 | 9855 | 7061 | 3397 | 11 | 40 | 19489 | 3491 | 3814 | 9 | 37 | 35 | 28027 | 15319 | 12141 | 13427 | 1000 | 1000 | 28337 | 28335 | 28327 | 28394 | 28293 |
62004 | 28096 | 213 | 0 | 18 | 0 | 0 | 18 | 0 | 1 | 1 | 0 | 1 | 0 | 4965 | 28257 | 0 | 1 | 0 | 16282 | 2004 | 1002 | 1000 | 1000 | 1000 | 5000 | 11928 | 10 | 0 | 0 | 22699 | 28377 | 28216 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 1000 | 28076 | 28382 | 1 | 1 | 61001 | 1000 | 1000 | 1 | 1000 | 0 | 3 | 1001 | 0 | 0 | 0 | 1000 | 0 | 3 | 3 | 0 | 0 | 13962 | 10327 | 6993 | 3414 | 8 | 38 | 19799 | 3341 | 3815 | 14 | 39 | 43 | 27808 | 14513 | 12524 | 13342 | 1000 | 1000 | 28033 | 28233 | 28227 | 28229 | 28237 |
62004 | 28500 | 213 | 0 | 19 | 0 | 0 | 13 | 0 | 0 | 0 | 26 | 1 | 0 | 4991 | 27951 | 0 | 1 | 1 | 16126 | 2000 | 1004 | 1000 | 1000 | 1000 | 5000 | 11943 | 9 | 0 | 0 | 22652 | 28262 | 28594 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 1000 | 28393 | 28217 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 0 | 2 | 1000 | 0 | 0 | 0 | 1000 | 1 | 3 | 3 | 0 | 0 | 13888 | 10168 | 7202 | 3462 | 10 | 38 | 19623 | 3387 | 3808 | 14 | 40 | 44 | 27998 | 14770 | 12567 | 13610 | 1000 | 1000 | 28157 | 28292 | 28344 | 28225 | 28267 |
62004 | 28322 | 212 | 0 | 13 | 0 | 0 | 16 | 0 | 0 | 0 | 4 | 1 | 0 | 5090 | 28042 | 0 | 1 | 1 | 16231 | 2004 | 1004 | 1000 | 1000 | 1000 | 5000 | 11947 | 12 | 0 | 0 | 22664 | 28482 | 28368 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 1000 | 28157 | 28205 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 0 | 3 | 1000 | 0 | 0 | 3 | 1003 | 1 | 0 | 3 | 0 | 0 | 13873 | 10391 | 7263 | 3230 | 12 | 36 | 19817 | 3424 | 3808 | 9 | 36 | 42 | 27991 | 14527 | 12274 | 13119 | 1000 | 1000 | 28200 | 28180 | 28161 | 28211 | 28316 |
62004 | 28230 | 212 | 0 | 16 | 0 | 0 | 20 | 0 | 0 | 0 | 232 | 1 | 0 | 5150 | 28229 | 1 | 1 | 1 | 16198 | 2000 | 1004 | 1000 | 1000 | 1000 | 5000 | 11907 | 8 | 0 | 0 | 22724 | 28240 | 28510 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 1000 | 28225 | 28313 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 0 | 3 | 1001 | 0 | 0 | 3 | 1001 | 2 | 3 | 3 | 0 | 0 | 13920 | 10536 | 7198 | 3481 | 8 | 31 | 19704 | 3319 | 3812 | 8 | 42 | 38 | 27971 | 14371 | 12413 | 13323 | 1000 | 1000 | 28314 | 28325 | 28466 | 28221 | 28281 |
62004 | 28376 | 211 | 0 | 17 | 0 | 0 | 16 | 0 | 0 | 0 | 29 | 0 | 0 | 5187 | 28068 | 1 | 1 | 0 | 16218 | 2004 | 1004 | 1000 | 1000 | 1000 | 5000 | 11900 | 9 | 0 | 0 | 22708 | 28138 | 28228 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 1000 | 28309 | 28377 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 0 | 3 | 1000 | 0 | 0 | 3 | 1000 | 2 | 0 | 3 | 0 | 0 | 13986 | 10368 | 7303 | 3425 | 7 | 32 | 19526 | 3414 | 3818 | 12 | 44 | 39 | 27883 | 14046 | 12381 | 13172 | 1000 | 1000 | 28228 | 28269 | 28255 | 28162 | 28490 |
Chain cycles: 3
Code:
ld1r { v0.8b }, [x6] fmov x0, d0 eor x8, x8, x0 eor x8, x8, x0 add x6, x6, x8
mov x0, 1 mov x1, 2 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 3 chain cycles): 11.0047
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 09 | 0e | 0f | 18 | 19 | 1e | 1f | 22 | 23 | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | ac | af | b5 | bb | l1d cache miss ld nonspec (bf) | c2 | branch cond mispred nonspec (c5) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
60205 | 140094 | 1049 | 0 | 0 | 1 | 1 | 0 | 0 | 424 | 0 | 1 | 0 | 140035 | 139410 | 129362 | 25 | 70100 | 40100 | 20003 | 10000 | 30242 | 20000 | 10000 | 1264045 | 6693685 | 14308701 | 140026 | 0 | 140035 | 140035 | 131832 | 3 | 132399 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 20000 | 140035 | 140035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 10000 | 2 | 37109 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 3210 | 1 | 122 | 1 | 1 | 139546 | 40000 | 0 | 6 | 9 | 10000 | 10000 | 40100 | 140051 | 140052 | 140157 | 140051 | 140036 |
60205 | 140079 | 1058 | 0 | 0 | 0 | 0 | 0 | 0 | 2299 | 0 | 1 | 0 | 140059 | 140640 | 130140 | 889 | 70483 | 40324 | 20100 | 10037 | 34327 | 23034 | 11477 | 1335237 | 6757146 | 14450528 | 142219 | 0 | 142895 | 143176 | 132434 | 474 | 133877 | 69526 | 35152 | 11599 | 22768 | 69762 | 11638 | 23095 | 142905 | 142704 | 31 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10045 | 1 | 10021 | 0 | 3 | 10001 | 0 | 0 | 0 | 2 | 0 | 0 | 3210 | 1 | 122 | 1 | 0 | 139546 | 40000 | 9 | 0 | 9 | 10000 | 10000 | 40100 | 140051 | 140379 | 140051 | 140051 | 140048 |
60204 | 140050 | 1052 | 1 | 1 | 0 | 0 | 3 | 10 | 916 | 440 | 0 | 0 | 140032 | 139410 | 129359 | 25 | 70102 | 40100 | 20002 | 10000 | 30100 | 20000 | 10000 | 1264045 | 6693538 | 14310633 | 140023 | 0 | 140035 | 140050 | 131792 | 3 | 132402 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 20000 | 140050 | 140047 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 3210 | 1 | 127 | 1 | 1 | 139552 | 40000 | 9 | 0 | 6 | 10000 | 10000 | 40100 | 140051 | 140036 | 140048 | 140051 | 140036 |
60204 | 140035 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 140035 | 139407 | 129347 | 25 | 70100 | 40100 | 20002 | 10000 | 30100 | 20000 | 10000 | 1263803 | 6692947 | 14310633 | 140026 | 0 | 140035 | 140047 | 131825 | 3 | 132402 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 20000 | 140050 | 140047 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 3 | 0 | 10000 | 0 | 0 | 1 | 0 | 0 | 0 | 3210 | 1 | 127 | 1 | 1 | 139546 | 40006 | 6 | 0 | 9 | 10000 | 10000 | 40100 | 140051 | 140051 | 140036 | 140036 | 140048 |
60204 | 140035 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 25 | 0 | 0 | 1 | 140032 | 139407 | 129362 | 25 | 70102 | 40100 | 20002 | 10000 | 30100 | 20000 | 10000 | 1264136 | 6692947 | 14311128 | 140011 | 0 | 140047 | 140036 | 131851 | 3 | 132382 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 20000 | 140050 | 140047 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10000 | 0 | 10000 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 3210 | 1 | 139 | 1 | 1 | 139546 | 40000 | 9 | 0 | 6 | 10000 | 10000 | 40100 | 140036 | 140036 | 140048 | 140036 | 140048 |
60204 | 140035 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 140020 | 139410 | 129362 | 25 | 70102 | 40100 | 20000 | 10002 | 30100 | 20000 | 10000 | 1264045 | 6693538 | 14310737 | 140026 | 0 | 140050 | 140050 | 131792 | 3 | 132403 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 20000 | 140035 | 140035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 3210 | 1 | 122 | 1 | 1 | 139552 | 40000 | 9 | 0 | 9 | 10000 | 10000 | 40100 | 140036 | 140051 | 140051 | 140051 | 140036 |
60204 | 140047 | 1049 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 140020 | 139410 | 129359 | 25 | 70102 | 40100 | 20002 | 10000 | 30100 | 20000 | 10000 | 1264136 | 6692995 | 14308701 | 140011 | 0 | 140035 | 140050 | 131792 | 3 | 132382 | 60100 | 30394 | 10000 | 20000 | 60200 | 10000 | 20000 | 140047 | 140047 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 0 | 0 | 0 | 3210 | 1 | 122 | 1 | 1 | 139546 | 40000 | 6 | 6 | 0 | 10000 | 10000 | 40100 | 140051 | 140051 | 140051 | 140051 | 140051 |
60204 | 140047 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 140032 | 139410 | 129362 | 25 | 70102 | 40100 | 20000 | 10000 | 30100 | 20000 | 10000 | 1264136 | 6693685 | 14311128 | 140011 | 0 | 140047 | 140050 | 131792 | 3 | 132402 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 20000 | 140050 | 140047 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 3210 | 1 | 122 | 1 | 1 | 139652 | 40000 | 6 | 6 | 0 | 10000 | 10000 | 40100 | 140048 | 140051 | 140051 | 140051 | 140048 |
60204 | 140050 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 140032 | 139406 | 129359 | 25 | 70102 | 40100 | 20000 | 10000 | 30100 | 20000 | 10000 | 1264045 | 6693538 | 14308701 | 140023 | 0 | 140035 | 140047 | 131837 | 3 | 132382 | 60100 | 30389 | 10000 | 20000 | 60200 | 10000 | 20000 | 140050 | 140047 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 10000 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 3210 | 1 | 127 | 1 | 1 | 139555 | 40000 | 6 | 6 | 9 | 10000 | 10000 | 40100 | 140051 | 140051 | 140051 | 140036 | 140051 |
60204 | 140050 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 140020 | 139410 | 129414 | 25 | 70102 | 40100 | 20002 | 10001 | 30100 | 20000 | 10000 | 1264045 | 6694114 | 14310945 | 140023 | 0 | 140047 | 140052 | 131857 | 3 | 132402 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 20000 | 140035 | 140035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 0 | 0 | 0 | 0 | 3210 | 1 | 127 | 1 | 1 | 139546 | 40000 | 9 | 6 | 0 | 10000 | 10000 | 40100 | 140048 | 140048 | 140051 | 140036 | 140036 |
Result (median cycles for code, minus 3 chain cycles): 11.0047
retire uop (01) | cycle (02) | 03 | 09 | 0e | 0f | 18 | 19 | 1e | 22 | 23 | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | int prf full (71) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | ac | af | b5 | l1d cache miss ld nonspec (bf) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
60025 | 140049 | 1048 | 1 | 0 | 0 | 7 | 5 | 1 | 1 | 0 | 140803 | 139798 | 129370 | 25 | 70012 | 40010 | 20002 | 10000 | 30010 | 20000 | 10000 | 1264443 | 6695410 | 14328846 | 0 | 140023 | 140047 | 140050 | 131815 | 0 | 3 | 132431 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 20000 | 140050 | 140035 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 1 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 3140 | 6 | 113 | 4 | 2 | 139554 | 40000 | 9 | 6 | 0 | 10000 | 10000 | 40010 | 140051 | 140036 | 140051 | 140051 | 140051 |
60024 | 140047 | 1048 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 140020 | 139394 | 129362 | 25 | 70012 | 40010 | 20002 | 10000 | 30010 | 20000 | 10000 | 1264443 | 6696274 | 14326216 | 0 | 140026 | 140050 | 140050 | 131818 | 0 | 3 | 132420 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 20000 | 140035 | 140035 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 1 | 0 | 10000 | 1 | 0 | 0 | 3140 | 2 | 113 | 4 | 5 | 139569 | 40000 | 0 | 0 | 9 | 10000 | 10000 | 40010 | 140036 | 140036 | 140048 | 140051 | 140051 |
60024 | 140035 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 140035 | 139397 | 129359 | 25 | 70012 | 40010 | 20002 | 10000 | 30010 | 20000 | 10000 | 1264443 | 6694963 | 14325931 | 0 | 140023 | 140035 | 140047 | 131803 | 0 | 3 | 132420 | 60010 | 30207 | 10000 | 20000 | 60020 | 10000 | 20000 | 140050 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 10000 | 0 | 1 | 0 | 3140 | 4 | 113 | 4 | 3 | 139566 | 40000 | 9 | 6 | 9 | 10000 | 10000 | 40010 | 140051 | 140036 | 140051 | 140051 | 140036 |
60024 | 140050 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 140032 | 139394 | 129362 | 25 | 70010 | 40010 | 20002 | 10000 | 30010 | 20000 | 10000 | 1264443 | 6697330 | 14325829 | 0 | 140026 | 140050 | 140047 | 131818 | 0 | 3 | 132498 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 20000 | 140047 | 140035 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 1 | 3140 | 2 | 113 | 2 | 4 | 139569 | 40000 | 9 | 9 | 9 | 10000 | 10000 | 40010 | 140148 | 140048 | 140051 | 140051 | 140051 |
60024 | 140050 | 1049 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 140035 | 139394 | 129359 | 25 | 70012 | 40010 | 20000 | 10000 | 30010 | 20000 | 10000 | 1264974 | 6693586 | 14321442 | 0 | 140011 | 140050 | 140035 | 131818 | 0 | 3 | 132433 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 20000 | 140050 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 3140 | 2 | 111 | 3 | 4 | 139569 | 40000 | 0 | 6 | 9 | 10000 | 10000 | 40010 | 140051 | 140048 | 140051 | 140036 | 140036 |
60024 | 140035 | 1049 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 140020 | 139397 | 129359 | 52 | 70010 | 40010 | 20000 | 10000 | 30010 | 20000 | 10000 | 1264888 | 6693538 | 14321442 | 0 | 140026 | 140050 | 140051 | 131818 | 0 | 3 | 132430 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 20000 | 140050 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 3140 | 5 | 113 | 3 | 5 | 139569 | 40000 | 0 | 0 | 0 | 10000 | 10000 | 40010 | 140036 | 140036 | 140048 | 140051 | 140048 |
60024 | 140047 | 1049 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 140020 | 139397 | 129362 | 25 | 70012 | 40010 | 20000 | 10000 | 30010 | 20000 | 10000 | 1264443 | 6696610 | 14326445 | 0 | 140026 | 140047 | 140050 | 131818 | 0 | 3 | 132430 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 20000 | 140050 | 140035 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 3140 | 4 | 113 | 4 | 4 | 139591 | 40000 | 6 | 6 | 0 | 10000 | 10000 | 40010 | 140051 | 140036 | 140051 | 140048 | 140051 |
60024 | 140050 | 1049 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 140035 | 139397 | 129362 | 25 | 70012 | 40010 | 20002 | 10000 | 30010 | 20000 | 10000 | 1264443 | 6697186 | 14325829 | 0 | 140026 | 140050 | 140050 | 131815 | 0 | 3 | 132433 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 20000 | 140050 | 140035 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 10000 | 0 | 1 | 0 | 3140 | 4 | 111 | 4 | 2 | 139558 | 40000 | 9 | 9 | 9 | 10000 | 10000 | 40010 | 140051 | 140048 | 140036 | 140048 | 140036 |
60024 | 140050 | 1049 | 0 | 0 | 0 | 0 | 0 | 13 | 1 | 0 | 140035 | 139397 | 129347 | 25 | 70012 | 40010 | 20000 | 10000 | 30010 | 20000 | 10000 | 1264429 | 6695698 | 14326112 | 0 | 140011 | 140047 | 140050 | 131818 | 0 | 3 | 132430 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 20000 | 140035 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 0 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 3140 | 3 | 111 | 3 | 5 | 139566 | 40000 | 6 | 6 | 6 | 10000 | 10000 | 40010 | 140036 | 140036 | 140036 | 140048 | 140048 |
60024 | 140035 | 1049 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 140035 | 139394 | 129362 | 25 | 70012 | 40010 | 20000 | 10000 | 30010 | 20000 | 10000 | 1264443 | 6695491 | 14326345 | 0 | 140011 | 140035 | 140050 | 131803 | 0 | 3 | 132433 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 20000 | 140035 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 10000 | 0 | 1 | 0 | 3140 | 4 | 113 | 4 | 2 | 139554 | 40000 | 0 | 0 | 9 | 10000 | 10000 | 40010 | 140051 | 140051 | 140051 | 140051 | 140048 |
Count: 8
Code:
ld1r { v0.8b }, [x6] ld1r { v0.8b }, [x6] ld1r { v0.8b }, [x6] ld1r { v0.8b }, [x6] ld1r { v0.8b }, [x6] ld1r { v0.8b }, [x6] ld1r { v0.8b }, [x6] ld1r { v0.8b }, [x6]
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.3341
retire uop (01) | cycle (02) | 03 | 09 | l2 tlb miss data (0b) | 0e | 0f | 1e | 1f | 22 | 23 | 3a | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | simd prf full (72) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d cache miss ld (a3) | a5 | ld unit uop (a6) | l1d cache writeback (a8) | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160205 | 26727 | 200 | 1 | 0 | 1 | 0 | 243 | 0 | 1 | 0 | 1 | 26706 | 2 | 12 | 12 | 19 | 25 | 160141 | 100 | 80045 | 80000 | 100 | 80020 | 80015 | 500 | 1170179 | 1884588 | 0 | 26709 | 26728 | 26728 | 6652 | 0 | 6 | 6677 | 160135 | 200 | 80020 | 80020 | 200 | 80020 | 80020 | 26708 | 26723 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 1 | 100 | 80000 | 39 | 0 | 80039 | 0 | 35 | 80039 | 6 | 0 | 35 | 43 | 1 | 1 | 1 | 5117 | 0 | 16 | 1 | 0 | 26725 | 10 | 6 | 0 | 80000 | 80000 | 100 | 26709 | 26724 | 26724 | 26729 | 26729 |
160204 | 26728 | 200 | 0 | 0 | 1 | 0 | 41 | 0 | 1 | 0 | 1 | 26719 | 0 | 0 | 12 | 16 | 25 | 160100 | 100 | 80045 | 80000 | 100 | 80020 | 80015 | 500 | 1175911 | 1887539 | 0 | 26709 | 26708 | 26708 | 6632 | 0 | 6 | 6677 | 160134 | 200 | 80020 | 80020 | 200 | 80020 | 80020 | 26831 | 26708 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 39 | 0 | 80039 | 0 | 0 | 80039 | 6 | 1 | 35 | 43 | 1 | 1 | 1 | 5117 | 0 | 16 | 0 | 0 | 26725 | 10 | 10 | 0 | 80000 | 80000 | 100 | 26729 | 26709 | 26729 | 26729 | 26729 |
160204 | 26728 | 200 | 0 | 0 | 0 | 1 | 41 | 0 | 0 | 0 | 1 | 26693 | 2 | 12 | 0 | 11 | 25 | 160141 | 100 | 80041 | 80000 | 100 | 80000 | 80000 | 500 | 1173183 | 1884444 | 0 | 26704 | 26728 | 26708 | 6630 | 0 | 3 | 6666 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 80000 | 26723 | 26723 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 0 | 80000 | 0 | 0 | 80039 | 0 | 1 | 0 | 43 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 26725 | 0 | 10 | 0 | 80000 | 80000 | 100 | 26709 | 26709 | 26729 | 26729 | 26729 |
160204 | 26728 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 26719 | 2 | 0 | 12 | 16 | 25 | 160145 | 100 | 80045 | 80000 | 100 | 80000 | 80000 | 500 | 1168754 | 1884011 | 1 | 26689 | 26708 | 26728 | 6650 | 0 | 3 | 6686 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 80000 | 26708 | 26708 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 39 | 0 | 80035 | 0 | 39 | 80039 | 0 | 1 | 35 | 39 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 26720 | 0 | 6 | 0 | 80000 | 80000 | 100 | 26729 | 26729 | 26729 | 26709 | 26729 |
160204 | 26728 | 200 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 0 | 1 | 26708 | 2 | 12 | 0 | 16 | 25 | 160100 | 100 | 80045 | 80000 | 100 | 80000 | 80000 | 500 | 1168880 | 1884011 | 1 | 26704 | 26723 | 26728 | 6630 | 0 | 3 | 6686 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 80000 | 26728 | 26723 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 39 | 0 | 80039 | 0 | 0 | 80039 | 6 | 1 | 39 | 43 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 26720 | 0 | 6 | 0 | 80000 | 80000 | 100 | 26729 | 26729 | 26729 | 26729 | 26709 |
160204 | 26728 | 200 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 0 | 1 | 26797 | 2 | 12 | 12 | 16 | 25 | 160100 | 100 | 80043 | 80000 | 100 | 80000 | 80000 | 500 | 1168880 | 1884011 | 0 | 26709 | 26728 | 26728 | 6630 | 0 | 3 | 6666 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 80000 | 26723 | 26723 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 39 | 0 | 80035 | 0 | 39 | 80035 | 6 | 1 | 39 | 39 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 26705 | 6 | 6 | 0 | 80000 | 80000 | 100 | 26709 | 26709 | 26729 | 26709 | 26729 |
160204 | 26728 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 26719 | 0 | 12 | 12 | 0 | 25 | 160141 | 100 | 80045 | 80000 | 100 | 80000 | 80000 | 500 | 1174628 | 1887328 | 1 | 26709 | 26728 | 26728 | 6630 | 0 | 3 | 6686 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 80000 | 26723 | 26723 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 39 | 0 | 80000 | 0 | 39 | 80039 | 6 | 0 | 35 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 26705 | 6 | 10 | 0 | 80000 | 80000 | 100 | 26709 | 26729 | 26724 | 26724 | 26729 |
160204 | 26728 | 200 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 0 | 1 | 26699 | 2 | 12 | 12 | 0 | 25 | 160145 | 100 | 80041 | 80000 | 100 | 80000 | 80000 | 500 | 1173183 | 1884444 | 1 | 26689 | 26728 | 26728 | 6650 | 0 | 3 | 6666 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 80000 | 26723 | 26708 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 0 | 80000 | 0 | 0 | 80000 | 6 | 0 | 39 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 26726 | 6 | 10 | 0 | 80000 | 80000 | 100 | 26709 | 26729 | 26729 | 26709 | 26729 |
160204 | 26728 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 26717 | 2 | 18 | 12 | 16 | 25 | 160141 | 100 | 80045 | 80000 | 100 | 80000 | 80000 | 500 | 1168754 | 1884011 | 0 | 26709 | 26708 | 26708 | 6650 | 0 | 3 | 6686 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 80000 | 26708 | 26723 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 39 | 0 | 80039 | 0 | 0 | 80039 | 6 | 1 | 35 | 39 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 26725 | 10 | 10 | 0 | 80000 | 80000 | 100 | 26741 | 26729 | 26709 | 26724 | 26729 |
160204 | 26708 | 200 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 0 | 1 | 26713 | 2 | 0 | 12 | 16 | 25 | 160100 | 100 | 80045 | 80000 | 100 | 80000 | 80000 | 500 | 1168880 | 1884011 | 0 | 26709 | 26723 | 26723 | 6630 | 0 | 3 | 6681 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 80000 | 26708 | 26708 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 1 | 100 | 80000 | 39 | 0 | 80039 | 0 | 39 | 80000 | 0 | 1 | 35 | 39 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 26725 | 10 | 6 | 0 | 80000 | 80000 | 100 | 26729 | 26724 | 26729 | 26724 | 26709 |
Result (median cycles for code divided by count): 0.3342
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 0e | 0f | 1e | 22 | 23 | 24 | 3a | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | 92 | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | cd | cf | d0 | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | db | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160025 | 26738 | 200 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 66 | 1 | 0 | 0 | 3 | 26732 | 0 | 7 | 9 | 22 | 25 | 160029 | 10 | 80064 | 80000 | 10 | 80000 | 80000 | 50 | 1167371 | 1886603 | 1 | 26696 | 26715 | 26737 | 6681 | 3 | 6695 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 80000 | 26715 | 26737 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 1 | 10 | 80020 | 20 | 45 | 80019 | 1 | 0 | 1 | 63 | 80169 | 6 | 1 | 59 | 43 | 19 | 1 | 0 | 5020 | 0 | 0 | 4 | 16 | 0 | 2 | 2 | 26734 | 13 | 13 | 2 | 80000 | 80000 | 10 | 26738 | 26738 | 26716 | 26738 | 26738 |
160024 | 26737 | 200 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 66 | 1 | 0 | 0 | 3 | 26703 | 0 | 7 | 7 | 20 | 25 | 160029 | 10 | 80065 | 80000 | 10 | 80000 | 80000 | 50 | 1170179 | 1887750 | 1 | 26723 | 26737 | 26739 | 6681 | 3 | 6695 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 80000 | 26715 | 26715 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80020 | 20 | 43 | 80019 | 0 | 0 | 1 | 61 | 80000 | 6 | 0 | 19 | 43 | 19 | 1 | 0 | 5020 | 0 | 0 | 2 | 16 | 0 | 2 | 2 | 26734 | 13 | 13 | 2 | 80000 | 80000 | 10 | 26718 | 26738 | 26738 | 26738 | 26716 |
160024 | 26737 | 200 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 67 | 1 | 0 | 0 | 3 | 26709 | 0 | 7 | 7 | 19 | 25 | 160074 | 10 | 80065 | 80000 | 10 | 80000 | 80000 | 50 | 1167371 | 1878937 | 1 | 26718 | 26715 | 26840 | 6805 | 3 | 6717 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 80000 | 26738 | 26737 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80020 | 20 | 43 | 80059 | 1 | 0 | 0 | 61 | 80040 | 6 | 1 | 58 | 43 | 19 | 0 | 0 | 5020 | 0 | 0 | 2 | 16 | 0 | 3 | 3 | 26734 | 13 | 0 | 1 | 80000 | 80000 | 10 | 26738 | 26716 | 26716 | 26738 | 26738 |
160024 | 26737 | 200 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 21 | 1 | 0 | 0 | 3 | 26735 | 3 | 0 | 0 | 21 | 25 | 160074 | 10 | 80065 | 80000 | 10 | 80000 | 80000 | 50 | 1168291 | 1883190 | 0 | 26718 | 26715 | 26715 | 6682 | 3 | 6695 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 80000 | 26737 | 26737 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80020 | 20 | 43 | 80060 | 1 | 0 | 0 | 21 | 80040 | 0 | 1 | 59 | 0 | 19 | 0 | 0 | 5020 | 0 | 0 | 3 | 16 | 0 | 3 | 3 | 26734 | 13 | 13 | 0 | 80000 | 80000 | 10 | 26716 | 26738 | 26738 | 26738 | 26738 |
160024 | 26737 | 200 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 67 | 0 | 0 | 0 | 3 | 26731 | 2 | 7 | 9 | 20 | 25 | 160029 | 10 | 80063 | 80000 | 10 | 80000 | 80000 | 50 | 1167722 | 1886406 | 0 | 26718 | 26737 | 26737 | 6682 | 3 | 6717 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 80000 | 26737 | 26737 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80021 | 19 | 43 | 80019 | 1 | 0 | 1 | 64 | 80040 | 6 | 0 | 58 | 43 | 19 | 1 | 0 | 5020 | 0 | 0 | 2 | 16 | 0 | 2 | 2 | 26713 | 13 | 13 | 2 | 80000 | 80000 | 10 | 26738 | 26716 | 26738 | 26716 | 26716 |
160024 | 26737 | 200 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 66 | 0 | 0 | 0 | 3 | 27378 | 0 | 7 | 0 | 20 | 25 | 160029 | 10 | 80019 | 80000 | 10 | 80000 | 80000 | 50 | 1169235 | 1878296 | 1 | 26718 | 26737 | 26737 | 6681 | 3 | 6717 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 80000 | 26737 | 26715 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80020 | 19 | 43 | 80193 | 1 | 0 | 1 | 60 | 80040 | 6 | 0 | 59 | 43 | 19 | 2 | 0 | 5020 | 0 | 0 | 2 | 16 | 0 | 2 | 3 | 26712 | 13 | 13 | 2 | 80000 | 80000 | 10 | 26738 | 26738 | 26738 | 26716 | 26738 |
160024 | 26737 | 200 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 66 | 1 | 0 | 0 | 3 | 26731 | 3 | 7 | 0 | 0 | 25 | 160073 | 10 | 80019 | 80000 | 10 | 80000 | 80000 | 50 | 1167722 | 1886409 | 1 | 26718 | 26737 | 26715 | 6681 | 3 | 6717 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 80000 | 26737 | 26737 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80019 | 20 | 43 | 80059 | 1 | 2 | 1 | 61 | 80039 | 6 | 1 | 19 | 43 | 19 | 0 | 0 | 5020 | 0 | 0 | 2 | 16 | 0 | 2 | 2 | 26734 | 13 | 13 | 2 | 80000 | 80000 | 10 | 26738 | 26738 | 26738 | 26716 | 26716 |
160024 | 26737 | 200 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 67 | 0 | 0 | 0 | 3 | 26709 | 3 | 0 | 7 | 1 | 25 | 160075 | 10 | 80065 | 80000 | 10 | 80000 | 80000 | 50 | 1169774 | 1878937 | 1 | 26718 | 26715 | 26737 | 6681 | 3 | 6717 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 80000 | 26737 | 26737 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80020 | 20 | 0 | 80058 | 0 | 0 | 0 | 61 | 80039 | 6 | 1 | 19 | 44 | 19 | 0 | 0 | 5020 | 9 | 0 | 2 | 16 | 0 | 2 | 2 | 26734 | 13 | 13 | 0 | 80000 | 80000 | 10 | 26739 | 26738 | 26738 | 26738 | 26738 |
160024 | 26737 | 201 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 21 | 0 | 0 | 0 | 3 | 26731 | 3 | 7 | 7 | 20 | 25 | 160029 | 10 | 80065 | 80000 | 10 | 80000 | 80000 | 50 | 1178590 | 1878937 | 1 | 26718 | 26737 | 26737 | 6682 | 3 | 6717 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 80000 | 26715 | 26737 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80020 | 20 | 43 | 80058 | 0 | 0 | 2 | 21 | 80042 | 6 | 0 | 58 | 0 | 19 | 2 | 0 | 5020 | 0 | 0 | 2 | 16 | 0 | 2 | 2 | 26734 | 13 | 13 | 0 | 80000 | 80000 | 10 | 26738 | 26738 | 26719 | 26738 | 26738 |
160024 | 26715 | 200 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 21 | 0 | 0 | 0 | 3 | 26730 | 3 | 7 | 0 | 0 | 25 | 160073 | 10 | 80063 | 80000 | 10 | 80000 | 80000 | 50 | 1168291 | 1877160 | 1 | 26718 | 26737 | 26737 | 6681 | 3 | 6717 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 80000 | 26737 | 26715 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 1 | 10 | 80019 | 20 | 0 | 80019 | 0 | 0 | 0 | 61 | 80040 | 0 | 1 | 19 | 43 | 19 | 0 | 0 | 5020 | 0 | 0 | 2 | 16 | 0 | 2 | 2 | 26737 | 13 | 13 | 1 | 80000 | 80000 | 10 | 26738 | 26738 | 26716 | 26738 | 26738 |