Firestorm: LD1R (post-index, 2D) measurements

Code:

  ld1r { v0.2d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.004

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	24	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
62005	29637	238	1	1	3	0	2	3	1	0	0	0	0	3	0	0	4621	28973	0	0	0	17451	3003	1000	1003	1000	1000	1000	1000	5000	5000	11957	5	0	0	22618	29216	29467	3	27	3000	1000	1000	2002	1000	29264	29318	1	1	61001	1000	1000	1001	2	0	1003	0	1	1	1000	2	1	0	1	1	0	13214	9491	6940	3181	1	44	20766	3327	3824	13	46	47	28661	1000	16034	13135	14368	1000	1000	1000	29142	29557	29449	29392	29353
62004	29519	236	0	1	0	0	0	1	1	0	0	0	0	3	0	0	4668	29025	0	0	0	17227	3004	1000	1003	1000	1000	1000	1000	5000	5000	11903	5	0	0	22618	29211	29292	3	10	3000	1000	1000	2000	1000	29286	29420	2	1	61001	1000	1000	1004	1	0	1001	0	2	1	1000	0	1	3	1	1	0	13194	9302	6974	3172	0	52	20733	3389	3819	13	49	46	28727	1000	16298	13239	14608	1000	1000	1000	29439	29432	29357	29425	29423
62004	29532	237	0	1	1	0	1	1	0	1	1	0	0	3	0	0	4776	28923	1	0	0	17435	3001	1000	1003	1000	1000	1000	1000	5000	5044	11933	4	1	0	22616	29303	29376	3	10	3000	1000	1000	2000	1000	29367	29307	1	1	61001	1000	1000	1002	1	2	1004	0	3	2	1001	3	1	4	1	1	0	13225	9346	6968	3143	1	47	20795	3316	3820	15	45	49	28690	1000	16167	13147	14291	1000	1000	1000	29420	29448	29362	29508	29525
62004	29361	237	0	1	2	0	0	2	1	0	0	0	0	3	0	0	4634	29006	0	0	0	17422	3007	1000	1005	1000	1000	1000	1000	5000	5000	11919	6	0	0	22655	29217	29506	3	27	3000	1000	1000	2000	1000	29380	29267	1	1	61001	1000	1000	1002	1	0	1002	0	0	2	1000	2	2	2	1	1	0	13230	9626	6976	3154	1	51	20799	3437	3820	13	44	47	28698	1000	15985	13085	14440	1000	1000	1000	29505	29453	29342	29398	29524
62004	29335	235	0	1	1	1	0	1	1	0	0	0	1	1	0	0	4667	28984	0	1	1	17335	3001	1000	1004	1000	1000	1000	1000	5000	5000	11942	6	1	0	22621	29318	29371	3	10	3000	1001	1000	2000	1000	29375	29339	1	1	61001	1000	1000	1001	0	0	1003	1	1	1	1000	2	2	0	1	0	0	13266	9361	6977	3203	1	48	20771	3245	3813	12	48	48	28744	1000	16258	13099	14533	1000	1000	1000	29406	29443	29356	29503	29481
62004	29295	236	0	1	1	0	0	1	0	0	0	0	1	1	0	0	4741	28962	0	1	1	17479	3003	1000	1001	1000	1000	1000	1000	5000	5000	11946	0	0	0	22673	29152	29319	3	10	3000	1001	1000	2000	1000	29351	29360	1	1	61001	1000	1000	1001	7	2	1002	0	1	1	1000	3	1	2	1	1	0	13416	9610	6968	3179	1	45	20706	3220	3822	4	48	47	28706	1000	16267	13407	14342	1000	1000	1000	29495	29433	29494	29342	29535
62004	29527	236	0	1	1	0	1	0	1	0	0	1	0	1	0	0	4756	28828	0	0	1	17807	3003	1000	1003	1000	1000	1000	1000	5000	5000	11908	0	0	0	22631	29169	29402	12	10	3000	1000	1000	2000	1000	29234	29338	1	1	61001	1000	1000	1002	2	4	1002	0	1	451	1000	2	1	4	1	3	0	13121	9318	6984	3122	0	47	20701	3328	3817	19	53	50	28680	1000	16087	13277	14376	1000	1000	1000	29360	29514	29407	29514	29350
62004	29422	235	0	1	1	0	0	1	2	1	0	1	0	5	88	0	4709	29021	0	0	1	17686	3003	1001	1004	1000	1000	1000	1000	5000	5001	11909	5	0	0	22593	29128	29453	7	10	3000	1000	1000	2000	1000	29226	29130	1	1	61001	1000	1000	1003	1	3	1005	0	0	1	1001	3	2	2	1	0	0	13183	9372	6904	3116	0	45	20655	3240	3820	11	42	42	28570	1000	16145	13131	14421	1000	1000	1000	29334	29364	29349	29296	29412
62004	29413	235	0	1	1	0	2	1	0	1	0	6	6	807	528	0	4728	28904	0	0	1	17455	3005	1001	1003	1000	1000	1002	1000	5000	5000	11944	7	0	0	22651	29197	29316	3	10	3000	1000	1000	2002	1000	29225	29176	2	1	61001	1000	1000	1004	2	2	1003	0	0	1	1001	2	1	3	1	1	0	13391	9300	6980	3184	0	52	20868	3315	3813	26	50	47	28736	1001	15928	13206	14180	1000	1000	1000	29430	29479	29416	29358	29458
62004	29256	236	0	1	0	0	1	2	1	1	1	0	0	135	0	0	4706	28898	0	0	1	17339	3003	1000	1004	1000	1000	1000	1000	5000	5000	11942	1	1	0	22625	29233	29355	3	10	3000	1000	1000	2000	1000	29282	29293	1	1	61001	1000	1000	1003	1	3	1002	0	1	1	1001	2	2	4	0	1	0	13207	9366	7006	3149	0	46	20723	3273	3814	8	42	38	28618	1000	16241	13163	14602	1000	1000	1000	29247	29332	29326	29294	29368

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1r { v0.2d }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0059

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5e	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60205	140118	1126	1	0	1	1	0	1	1	1	0	0	2	0	1	0	1	140038	139577	25	80104	50100	20004	10000	40100	20000	10000	1245664	5304601	10710678	0	1	0	140029	0	140056	140054	131970	3	132435	70100	30200	10000	20000	60200	20000	20000	140053	140053	1	1	50201	100	99	100	40100	10000	10000	1	100	10001	2	1	10002	0	0	0	1	10000	1	1	1	1	0	3210	0	0	1	93	1	1	139718	50000	9	6	6	10000	10000	50100	140057	140054	140054	140057	140057
60204	140062	1125	1	0	1	1	0	1	0	0	0	0	5	0	0	0	0	140026	139575	25	80104	50100	20004	10000	40100	20000	10000	1246580	5304717	10710678	0	0	0	140029	0	140057	140056	131970	3	132422	70100	30200	10000	20000	60200	20000	20000	140056	140056	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	1	10002	0	0	0	268	10000	1	1	1	1	0	3210	0	0	2	93	1	1	139717	50000	6	6	9	10000	10000	50100	140054	140054	140054	140054	140054
60204	140053	1125	1	0	1	1	0	0	1	1	0	0	23	0	0	0	1	140039	139575	25	80104	50100	20004	10000	40100	20000	10000	1245664	5304753	10707382	0	0	0	140017	0	140053	140053	131970	3	132437	70100	30200	10000	20000	60200	20000	20000	140053	140053	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	2	1	10001	0	0	0	283	10001	1	1	0	1	0	3210	0	0	1	100	1	1	139713	50000	9	6	7	10000	10000	50100	140057	140057	140054	140054	140148
60204	140114	1125	1	0	1	0	0	0	0	0	0	0	5	0	0	0	1	140026	139739	25	80104	50100	20004	10000	40100	20000	10000	1245673	5304601	10710678	0	0	0	140017	0	140053	140041	131967	3	132425	70100	30200	10000	20000	60200	20000	20000	140054	140054	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	2	1	10002	0	0	0	466	10001	0	1	1	1	1	3210	0	0	2	93	1	1	142046	50000	10	10	6	10000	10000	50100	140042	140132	140057	140057	140055
60204	140068	1125	1	0	1	1	0	0	0	0	0	0	8	0	0	0	1	140041	139577	25	80104	50100	20004	10000	40100	20000	10000	1245673	5304601	10710678	0	0	0	140029	0	140053	140053	131967	3	132435	70100	30200	10000	20000	60200	20000	20000	140041	140053	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10001	0	0	0	289	10000	0	1	1	1	0	3210	0	0	1	93	1	1	139717	50000	9	8	6	10000	10000	50100	140057	140054	140057	140057	140058
60204	140100	1125	1	0	1	0	0	0	0	0	0	0	5	0	0	0	1	140041	139574	39	80104	50100	20004	10000	40100	20000	10000	1245736	5304601	10716271	0	0	0	140029	0	140057	140053	131995	3	132434	70100	30200	10000	20000	60200	20000	20000	140041	140041	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10001	0	1	0	7	10000	1	1	0	1	0	3210	0	0	1	93	1	1	139713	50000	9	6	0	10000	10000	50100	140054	140057	140057	140043	140054
60204	140119	1125	1	0	1	1	0	0	0	0	0	0	5	0	0	1	0	140026	139574	25	80104	50100	20004	10001	40100	20000	10000	1245664	5304718	10710754	0	0	0	140032	0	140056	140056	131967	3	132437	70100	30200	10000	20000	60452	20000	20000	140053	140056	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	2	1	10001	0	0	3	286	10000	1	1	1	1	0	3210	0	0	1	93	1	1	139719	50000	9	6	6	10000	10000	50100	140056	140055	140054	140054	140057
60204	140092	1125	1	0	0	1	0	1	0	1	0	1	23	0	0	1	1	140026	139574	50	80104	50100	20004	10000	40100	20000	10000	1245691	5304601	10710678	0	0	0	140032	0	140053	140055	131968	3	132437	70100	30200	10000	20000	60200	20000	20000	140053	140056	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	1	10001	0	0	0	286	10000	1	1	0	1	0	3235	0	0	1	93	1	1	139713	50000	9	6	6	10000	10000	50100	140054	140057	140057	140054	140057
60204	140131	1125	1	0	0	0	0	0	0	0	0	0	5	0	0	0	1	140038	139588	25	80102	50100	20002	10000	40100	20000	10000	1245682	5304720	10710678	0	0	0	140032	0	140055	140057	131970	3	132476	70100	30200	10000	20000	60484	20000	20000	140056	140053	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	1	1	10001	0	0	0	3220	10000	1	1	1	1	1	3210	0	0	1	93	2	1	139793	50010	11	6	11	10000	10000	50100	140141	140054	140143	140057	140057
60204	140325	1125	1	0	2	1	0	0	1	0	23	23	413	264	0	0	1	140321	139871	126	80129	50133	20013	10003	40382	20318	10116	1252168	5305149	10741927	0	0	0	140244	0	140224	140402	132054	34	132521	70617	30448	10080	20163	60688	20240	20163	140320	140239	4	1	50201	100	99	100	40100	10000	10000	0	100	10004	4	1	10004	0	0	3	424	10000	1	1	1	1	0	3210	0	0	1	93	1	1	139717	50000	6	6	10	10000	10000	50100	140042	140057	140054	140054	140057

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	18	19	1e	1f	22	23	24	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60025	140050	1085	0	0	0	0	1	0	1	0	0	0	0	0	140035	139654	51	80026	50010	20002	10000	40010	20000	10000	1245788	5307504	10716479	1	140023	140050	140047	132056	3	132458	70010	30020	10000	20000	60020	20000	20000	140052	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	3140	0	4	88	8	5	139721	50000	9	0	8	10000	10000	50010	140051	140051	140051	140144	140145
60024	140225	1087	0	0	0	0	3	2	274	88	0	0	0	0	140200	139770	128	80026	50038	20006	10002	40433	20161	10079	1250179	5311305	10725238	0	140159	140148	140421	132083	305	133994	70269	30382	10041	20331	60744	20080	20240	140210	140314	3	1	50021	10	9	10	40010	10000	10000	0	10	10004	2	1	10003	0	0	9578	10003	1	1	0	0	3140	0	8	88	8	5	139718	50000	9	6	9	10000	10000	50010	140051	140051	140051	140051	140051
60024	140035	1086	0	0	0	0	0	0	13	0	0	0	0	0	140020	139639	25	80012	50010	20002	10000	40010	20000	10000	1245797	5307582	10717109	0	140026	140053	140050	132035	3	132458	70010	30020	10000	20000	60020	20000	20000	140050	140049	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	1	0	0	10000	1	1	0	0	3140	0	8	88	8	8	139721	50000	9	6	9	10000	10000	50010	140036	140051	140051	140051	140051
60024	140050	1086	0	0	0	0	0	0	4	0	0	0	0	0	140035	139654	25	80012	50010	20002	10000	40010	20000	10000	1245806	5307504	10717109	1	140033	140050	140050	132026	3	132458	70010	30020	10000	20000	60020	20000	20000	140050	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	3	10000	1	1	0	0	3140	0	7	88	5	8	139719	50000	9	6	9	10000	10000	50010	140051	140051	140036	140036	140051
60024	140050	1085	0	0	0	0	0	0	13	0	0	0	0	0	140037	139654	25	80012	50010	20002	10000	40010	20000	10000	1245788	5306922	10717109	1	140026	140050	140035	132048	3	132458	70010	30020	10000	20000	60020	20000	20000	140050	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	1	0	3	10000	1	1	0	0	3140	0	8	88	7	8	139721	50009	9	9	9	10000	10000	50010	140036	140036	140051	140051	140053
60024	140035	1086	0	0	0	0	0	0	1	0	0	0	0	0	140035	139657	25	80012	50017	20006	10000	40010	20000	10000	1245761	5307504	10717343	0	140023	140052	140050	132038	3	132443	70010	30020	10000	20000	60020	20000	20000	140048	140050	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	3	10000	1	1	0	0	3140	0	4	88	11	7	139721	50000	9	9	9	10000	10000	50010	140482	140036	140036	140137	140051
60024	140050	1085	0	1	0	0	0	0	124	0	0	0	0	0	140035	139639	25	80012	50010	20002	10000	40010	20000	10000	1245788	5307504	10717109	1	140028	140050	140050	131995	3	132458	70010	30020	10000	20000	60020	20000	20000	140035	140035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	3	10000	1	1	0	0	3140	0	8	88	7	5	139721	50000	9	9	9	10000	10000	50010	140051	140054	140052	140051	140054
60024	140050	1086	0	0	0	0	0	0	1	0	1	0	0	0	140035	139654	25	80012	50010	20002	10000	40010	20000	10000	1245761	5307504	10717109	0	140026	140050	140035	131998	3	132458	70010	30020	10000	20000	60020	20000	20000	140051	140053	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	3140	0	4	88	6	6	139721	50000	9	9	9	10000	10000	50010	140051	140051	140051	140051	140051
60024	140050	1085	0	1	0	1	0	0	1	0	0	0	0	0	140020	139639	25	80012	50010	20002	10000	40010	20000	10000	1245788	5306922	10717109	0	140011	140050	140047	131995	3	132458	70010	30020	10000	20000	60020	20000	20000	140050	140047	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	3140	0	8	88	5	7	139718	50000	9	9	9	10000	10000	50010	140052	140051	140036	140051	140223
60024	140220	1088	1	0	1	1	3	2	265	176	0	0	0	1	142117	140518	51	80025	50020	20009	10002	40294	20157	10116	1247878	5313018	10725219	0	140166	140211	140237	132195	13	132540	71052	30265	10122	20166	60764	20162	20243	140222	140269	3	1	50021	10	9	10	40010	10000	10000	0	10	10003	2	1	10002	0	2	6345	10002	1	1	0	0	3140	0	8	88	5	7	139706	50000	6	9	9	10000	10000	50010	140051	140051	140051	140052	140051

Test 3: throughput

Count: 8

Code:

  ld1r { v0.2d }, [x6], x8
  ld1r { v0.2d }, [x6], x8
  ld1r { v0.2d }, [x6], x8
  ld1r { v0.2d }, [x6], x8
  ld1r { v0.2d }, [x6], x8
  ld1r { v0.2d }, [x6], x8
  ld1r { v0.2d }, [x6], x8
  ld1r { v0.2d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160205	80041	599	1	0	1	0	0	0	0	0	32	0	0	0	1	80026	0	6	6	250	25	240131	80100	80032	80000	80100	80000	80000	4358982	3758824	4918894	1	80022	80041	80041	59924	3	59999	240100	200	80000	80000	200	160000	80000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80006	8	23	80026	2	0	26	80019	6	1	26	23	7	1	5110	2	16	1	2	80038	0	80000	9	9	80000	80000	80100	80042	80042	80042	80042	80042
160204	80041	621	1	0	0	0	1	1	0	0	32	0	0	0	0	80026	0	6	6	10	25	240131	80100	80032	80000	80100	80000	80000	4359014	3758824	4918897	1	80022	80041	80041	59924	3	59999	240100	200	80000	80000	200	160000	80000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80006	7	0	80024	0	0	28	80018	6	1	26	0	6	0	5112	1	16	2	1	80038	0	80000	9	9	80000	80000	80100	80042	80042	80042	80042	80042
160204	80041	620	1	0	1	0	0	0	0	0	44	0	0	0	1	80026	1	6	0	2	25	240131	80193	80031	80000	80100	80000	80000	4358982	3758824	4918899	1	80022	80041	80041	59924	3	59999	240100	200	80000	80000	200	160000	80000	80041	80041	1	1	80201	100	99	100	100	80000	80000	4	100	80008	6	0	80027	1	1	26	80000	6	1	25	0	6	1	5110	2	16	2	1	80038	1	80000	9	9	80000	80000	80100	80042	80042	80042	80042	80042
160204	80041	621	1	1	0	1	0	0	0	0	43	0	0	0	0	80026	1	6	6	10	25	240107	80100	80031	80000	80100	80000	80000	4358986	3758824	4918896	1	80022	80041	80041	59995	3	59999	240100	200	80000	80000	200	160000	80000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80006	8	23	80026	0	0	7	80018	0	1	25	23	7	1	5112	1	16	1	2	80038	0	80000	9	0	80000	80000	80100	80042	80042	80042	80042	80042
160204	80041	621	1	1	0	0	1	0	0	0	31	0	0	0	0	80157	0	6	0	10	25	240131	80100	80031	80000	80100	80000	80000	4358970	3758825	4918894	1	80022	80041	80041	59924	3	59999	240100	200	80000	80000	200	160000	80000	80041	80041	1	1	80201	100	99	100	100	80000	80000	4	100	80007	7	26	80007	1	0	28	80019	6	1	7	23	6	0	5112	2	16	2	1	80038	1	80000	9	9	80000	80000	80100	80042	80042	80042	80042	80042
160204	80041	621	1	1	0	1	0	0	0	0	31	0	0	0	1	80026	1	6	6	14	25	240132	80100	80030	80000	82199	83869	81625	4358986	3758824	4918893	1	80022	80041	80041	59978	3	59999	240100	200	80000	80000	200	160000	80000	80041	80041	1	1	80201	100	99	100	100	80000	80000	4	100	80008	7	23	80025	0	0	29	80018	6	0	6	0	7	0	5112	2	16	2	1	80038	1	80000	9	9	80000	80000	80100	80042	80042	80042	80042	80042
160204	80041	621	1	0	0	0	0	0	0	0	31	0	0	0	1	80026	1	6	0	10	25	240132	80100	80031	80000	80100	80000	80000	4358954	3758823	4919014	1	80022	80041	80041	59924	3	59999	240100	200	80000	80000	200	160000	80000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80007	7	23	80026	0	1	7	80018	6	0	25	23	7	0	5112	2	16	2	1	80038	0	80000	9	0	80000	80000	80100	80042	80042	80042	80042	80042
160204	80041	620	1	0	1	0	0	0	0	0	31	0	0	0	0	80026	1	6	6	10	25	240132	80100	80031	80000	80100	80000	80000	4358982	3758824	4924422	1	80022	80041	80041	59924	3	59999	240100	200	80000	80000	200	160000	80000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80006	8	23	80025	0	0	26	80019	6	1	25	0	6	0	5112	2	16	1	2	80038	0	80000	12	9	80000	80000	80100	80042	80042	80042	80042	80042
160204	80041	620	1	0	1	0	0	0	0	0	175	0	0	0	1	80026	0	6	6	11	25	240132	80100	80031	80000	80100	80000	80000	4358982	3758824	4918896	1	80022	80041	80041	59987	3	59999	240100	200	80140	80000	200	160000	80000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80007	7	23	80026	1	0	25	80109	6	1	25	0	7	1	5112	2	16	2	2	80146	0	80000	9	9	80000	80000	80100	80042	80042	80042	80042	80042
160204	80041	620	1	1	1	0	0	0	0	0	32	0	0	0	0	80026	1	6	6	12	25	240131	80100	80007	80000	80100	80000	80000	4362261	3758824	4918898	1	80022	80041	80041	59924	3	59999	240100	200	80000	80000	200	160000	80000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80096	8	23	80025	0	1	28	80019	6	1	26	23	6	0	5110	2	16	2	2	80038	1	80000	0	10	80000	80000	80100	80042	80042	80042	80042	80042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160025	80041	643	1	0	1	0	0	1	1	0	0	0	42	0	0	0	0	80026	1	0	6	15	25	240046	80010	80036	80000	80010	80000	80000	4358385	3758820	4918912	0	0	80022	0	80041	80041	59946	3	60021	240010	20	80000	80000	20	160000	80000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80006	8	28	80032	0	0	0	30	80023	6	1	33	27	6	0	0	5020	2	16	0	0	0	2	2	80038	0	80000	13	13	80000	80000	80010	80042	80042	80042	80042	80042
160024	80041	643	1	0	0	0	0	0	0	0	0	0	35	0	0	0	0	80026	1	6	6	3	25	240017	80010	80035	80000	80010	80000	80000	4358377	3758824	4918424	0	0	80022	0	80041	80041	59946	3	60021	240010	20	80000	80000	20	160000	80000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80007	6	27	80030	0	1	0	29	80023	0	0	7	0	6	2	0	5020	2	16	0	0	0	2	2	80038	0	80000	13	0	80000	80000	80010	80042	80042	80042	80042	80042
160024	80041	643	1	0	0	1	0	0	0	1	0	0	36	0	0	0	0	80026	0	6	6	9	25	240046	80010	80035	80000	80010	80000	80000	4358377	3758820	4918910	0	0	80022	0	80041	80041	59946	3	60021	240010	20	80000	80000	20	160000	80000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80008	7	27	80009	0	0	0	7	80110	0	0	30	27	7	0	0	5020	2	16	0	0	0	2	2	80038	1	80000	13	13	80000	80000	80010	80042	80042	80042	80042	80042
160024	80041	643	1	0	0	1	0	1	1	1	0	0	59	0	0	0	1	80026	0	6	6	11	25	240045	80010	80007	80000	80010	80000	80000	4358433	3758824	4918911	0	0	80022	0	80177	80041	59946	3	60021	240010	20	80000	80000	20	160000	80000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80007	6	28	80007	2	1	0	30	80022	6	1	7	28	6	0	0	5020	2	16	0	0	0	2	2	80038	1	80000	13	13	80000	80000	80010	80042	80042	80042	80042	80042
160024	80041	642	1	0	1	0	0	2	0	0	0	0	42	0	0	0	1	80026	1	0	0	10	25	240016	80104	80216	80090	80010	80000	80000	4358377	3758824	4918906	0	0	80022	0	80041	80041	59946	3	60021	240010	20	80000	80000	20	160000	80000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80008	6	0	80029	2	0	0	7	80000	6	1	29	0	7	0	0	5020	2	16	0	0	0	2	2	80038	0	80000	13	15	80000	80000	80010	80042	80042	80042	80042	80042
160024	80041	643	1	0	0	0	0	1	1	0	0	0	19	0	0	0	0	80026	1	6	6	11	25	240046	80010	80035	80000	80010	80000	80000	4358433	3758824	4918424	0	0	80022	0	80041	80041	59946	3	60021	240010	20	80000	80000	20	160000	80000	80041	80175	1	1	80021	10	9	10	10	80000	80000	0	10	80008	8	0	80029	0	0	8	29	80023	6	1	30	32	7	1	0	5020	2	16	0	0	0	2	2	80146	0	80000	13	13	80000	80000	80010	80042	80042	80042	80042	80042
160024	80041	643	1	0	0	0	0	1	0	1	0	0	35	0	1	0	0	80026	1	6	6	14	25	240045	80010	80035	80000	80010	80000	80000	4358381	3758824	4918906	0	0	80022	0	80041	80041	59946	3	60021	240010	20	80000	80000	20	160000	80000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80007	7	27	80030	1	0	0	30	80023	6	0	7	0	6	0	0	5020	2	16	0	0	0	2	2	80038	0	80000	13	13	80000	80000	80010	80042	80042	80042	80042	80042
160024	80041	642	1	0	1	0	0	1	1	1	1	0	7	0	0	0	0	80026	0	6	6	5	25	240045	80010	80035	80000	80010	80140	80000	4358433	3758825	4918911	0	5	80022	3	80041	80041	59946	22	60021	240010	20	80000	80000	20	160000	80000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80008	6	0	80007	0	1	0	29	80023	6	1	29	0	7	0	0	5020	2	16	0	0	0	2	2	80038	1	80000	13	13	80000	80000	80010	80042	80042	80042	80042	80042
160024	80041	643	1	0	0	0	0	0	0	0	0	0	47	0	0	0	0	80026	1	6	6	14	25	240017	80010	80035	80000	80010	80000	80000	4358433	3758823	4918914	0	0	80022	0	80041	80041	59946	3	60021	240010	20	80000	80000	20	160000	80000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80006	7	30	80029	0	0	0	32	80022	6	1	6	27	7	2	0	5020	2	16	0	0	0	2	2	80038	0	80000	0	0	80000	80000	80010	80042	80042	80042	80042	80042
160024	80041	643	1	0	1	0	0	0	0	0	0	0	7	0	0	0	0	80026	1	0	6	1	25	240298	80010	80006	80000	80010	80000	80000	4358377	3758824	4918900	0	0	80129	0	80041	80041	59946	3	60021	240010	20	80000	80000	20	160000	80000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80008	6	27	80029	0	0	0	29	80023	0	1	29	27	6	0	0	5020	2	16	0	0	0	2	2	80038	0	80092	13	13	80000	80000	80010	80042	80042	80042	80042	80042

LD1R (post-index, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations