Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1R (post-index, 2S)

Test 1: uops

Code:

  ld1r { v0.2s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.003

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.002

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f18191e1f22243a3f43464951schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)5e5f60696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd load (98)inst ldst (9b)9dl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2c9cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
620052900923202901330100042701047422858411216773300310001004100010001000100050005000119430130226812876729008310300010001000200010002887928831116100110001000010000310010001100010000013179926468443131127120344315838061865692821710001555912427140611000100010002874429124290362891228878
6200429070232022002200000300048582845600016948300310001003100010001000100050005000119320140225932885428971310300010001000200010002870828654116100110001000010000310000004100320300013300931868413119136920296318838062674742820410001571012851142221000100010002869528729288432882728914
62004289852340280023001002800047592844410116964300310001003100010001000100050005002119070100226082871828742310300010001000200010002876728850116100110001000010000310010004100121300013195935768973169157320275322438081779762826110001568412821141341000100010002890228905290142887129000
6200428934233026002800000130004670284880101683530001000100010001000100010005000500011906060226102867128929310300010001000200010002877828901116100110001000010000010010100100120300013163940068633124147420388325538122667652835210001548212770139691000100010002891128912290992882428870
62004288382330240024000001300046662841400116982300310001000100010001000100050005000119380110226802876829027310300010001000200010002887428815116100110001000010000310010001100131300013166936368543131157520426319838052065802831310001563512938136501000100010002897628902288852891328961
6200429001232024002600000000048512845001016877300310001000100010001000100050005000119350120225642879928912310300010001000200010002887428914116100110001000010000210030001100023000013049934169573118156820207325138081572672833210001579612894140571000100010002896328890289172901728972
6200429020233024003000000280004687285681101682330031000100010001000100010005000500211902012022684287972885931030001000100020001000287372886621610011000100001000001000000110012030001321692556849312497820322326138081777762839810001575412798140381000100010002900028972288332896628826
62004290222320270028010001300046852847201016821300010001003100110001000100050005000119020120226282875228974310300010001000200010002889728766116100110001000110013310050023100203000013161936068983158146920330321238142975722835810001526112902141681000100010002899228991289982894928626
62004289152320270020000001100045482851001016829300310001000100010001000100050005002119030110226722886828962310300010001000200010002875728799116100110001000010000310000100100321300013187937869343120127520351320938102073682827410001542312883140131000100010002891129052289892896528823
62004290502310240028000001300047502851811116974300310001003100010001000100050005000119400110226062881328883310300010001000200010002876328776116100110001000010000310010001100100300013253939268533192117220177328238052068712834210001594912700140921000100010002893228912290252881428834

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1r { v0.2s }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0060

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f23243a3f4d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst simd alu (9a)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
60205140678113000001000340759800014002613958025801045010020002100004010020000100001245727530486710710990014002714015814005113196831324427010030200100002000060200200002000014005814003531502011009910040100100004100001100100002711100000000100001000000032101931113971850000131013100001000050100140041140055140055140055140052
6020414003511250000110090000140039139575258010250100200021000040100200001000012456735304639107105990140084140054140054131949313241670100302001000020000602002000020000140054140051115020110099100401001000001000001001000001100000100100001000000032101931113971850000131013100001000050100140056140058140055140056140055
602041400541125000010009000014004013957525801025010020002100004010020000100001245673530467810710759014010314005414005413196831324367010030200100002008260200200002000014005414013511502011009910040100100000100000100100110010000000318010000101000003210193111397995000013140100001000050100140121140052140055140148140055
602041401501085000000011330000140039139575258010250111200021000240100200791000012456825306787107105220140088140054140145132011131324357010030320100002008060200200822000014005414013911502011009910040100100000100000100100010110000000324510000101020003210193121398035001101013100001000050100140149140036140147140036140052
60204140054108601000010188000140036139556258010250100200021000040100200001000012456465304639107105220140039140035140035131968313243270100302001000020000602002000020000140054140054115020110099100401001000001000001001000000100000000100001010000032101931113971850000131013100001000050100140055140056140055140055140052
6020414003510860000000018800014003913957550801025011020002100004024320000100391245673530623710710522014011914005414012013200414132435701003032410000200006044020000200811400551400541150201100991004010010000010000010010001011000020032451000010100000323411232113971850000101313100001000050100140055140141140055140141140150
6020414005410870000100013300001401351397315080102501002000210000402412000010040124567353050721070927601400331401451400541319683132477703573020010040200006044220000200001400541400542150201100991004010010000010000010010000011000100001000110100000323411012113979450000131010100001000050100140036140055140055140055140052
6020414005410850000000010000140039139576258010250100200021000040100200001000012456735304639107106000140116140054140054131968313243570100302001000020000602002000020000140054140054115020110099100401001000001000001001000001100000000100001010000032101931113971950000131013100001000050100140055140055140055140052140052
60204140054108500000011181598001140041139577258010450100200041000040106200111000712458055305071107114600140026140035140050132024613250070123302191000720014602382001420014140050140047115020110099100401001000001000011001000001100000103100001000011132180160013977750000969100001000050100140142140052140053140051140151
602041402451131000000021388000140035139568258010250100200021000040106200111000612473345304845107100550140031140051140050132039613250082084302191004820014604862001420014140053140047315020110099100401001000001000001001000101100010703259100001010010032101931213972550000131010100001000050100140061140159140061140155140058

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0060

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f18191e1f2223243a3f4d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
600251401621086100001110146000001400451396452580014500102000210000401612000010000124582153078091071788900140036140060140060132008313246570010300201000020000600202000020000140057140057115002110910400101000010000010100021110002014100001101103141168814141398745000010010100001000050010140158140061140061140060140061
600241400571085100010100200000140026139661258001450010200041000040010200001000012458785307810107181200014003314005814006013200531324657001030020100002000060020200002000014004114005711500211091040010100001000001010002311000200110000111100314115887111397325000013100100001000050010140058140061140061140104140061
60024140071112510101110014301000140046139664258001450010200041000040010200001000012458785307110107178890014003314005714006113201131324667001030020100002000060020200002000014005914005811500211091040010100001000001010002211000100110000011110314188818121397125000010013100001000050010140058140061140063141238140061
6002414005711251010001001430100114004513966525800125001020002100004015120000100001245851530788410717889001400331400411400571319903132450700103002010000200006002020000200001400571400611150021109104001010000100000101000621100010111000001110031411288151413972950000131010100001000050010140061140058140061140059140058
600241400601125100001100501000140044139645258001450010200041000040010200001000012458515308578107222240014001714014614006013200531324687001030020100002000060020200002008114006614004111500211091040010100001000001010002211000510110000111110314188815161397325000001010100001000050010140061140058140061140061140162
60024140057112510000110117000011400261396615180014500102000210000400102000010000124586053077701071788900140036140060140060132009313248870010300201000020000600202000020000140061140058115002110910400101000010000010100022110002011100001111103141887151413973250000101310100001000050010140061140058140058140147140060
600241400411125101010000230000014004513966125800145001020002100004001020000100001245887530777010717889001400331400611400601320093132468700103002010000200006002020000200001400601400571150021109104001010000100000101000311100020111000011110031411287812139712500001000100001000050010140042140058140042140042140042
60024140041112510101010040010114004513964725800145001020004100004001020000100001245851530796210717454001400361400601400571320053132468700103002010000200806002020000200001400591400601150021109104001010000100000101000211100010071000011110031411688141413973150000101310100001000050010140042140065140061140061140061
600241400601126101000100140000014004513966425800285001020002100004001020000100001245878530792210717967001400171400581400571320363132468700103002010000200006002020000200001400411401391150021109104001010000100000101000111100030211000011111031411488141413972850000101313100001000050010140061140058140059140058140061
600241400601125101000100500100140045139664258001450010200041000040010200001000012458215307884107178890014003314006014005713200531324687001030020100002000060020200002000014005714005711500211091040010100001000001010002211000201410000110100314112881681397315000001113100001000050010140061140061140058140061140059

Test 3: throughput

Count: 8

Code:

  ld1r { v0.2s }, [x6], x8
  ld1r { v0.2s }, [x6], x8
  ld1r { v0.2s }, [x6], x8
  ld1r { v0.2s }, [x6], x8
  ld1r { v0.2s }, [x6], x8
  ld1r { v0.2s }, [x6], x8
  ld1r { v0.2s }, [x6], x8
  ld1r { v0.2s }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)0e0f18191e1f2223243f4346494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)c2cdcfd5map dispatch bubble (d6)dbddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602058004162100100021010080026166162524011980100801058000080244800008000043590183758824491865608002208004180041599243599992401002008000080000200160000800008004180041118020110099100100800008000011008000001480000001580009010000511031613380038180000968000080000801008004280042800428004280176
16020480041620001100120100800260606252401168010080018800008010080000801364359018375882449186700800220800418004159924359999240100200800008000020016000080000800418004111802011009910010080000800000100800000148000000168001260131400511031603380038180000008000080000801008004280173800428004280042
1602048004162100010019000080026160625240100801008001980000801008000080000435901837588244918518180022080041800415992435999924010020080000801442001600008000080041800411180201100991001008000080000010080000014800000008000000131700511021604380038180000978000080000801008004280042800428004280042
1602048004162100000019000080026160598240119801008000080000801008000080000435900637588244918671080022080041800415992435999924010020080000800002001600008000080041800411180201100991001008000080000110080000217800130013800140001700511031603280038080000008000080000801008004280042800428004280042
1602048004162100000019010080026006625240119801008008880000801008000080000435901037588244918518080022080041800415992435999924010020080000800002001600008000080174800411180201100991001008000080000010080000014800090017800106113000511031603280038180000908000080000801008004280042800428004280042
16020480041621000000132000080026160625240116801008001980000801008000080000435900637588244918671080022080041800415992435999924010020080000800002001600008000080041800411180201100991001008000080000010080000014800000012800000001700511031603380144080000078000080000801008017680042800428004280042
16020480041620000032280000800261005325240119801008037980000801008000080000435899037588244918518180022080041800415992435999924010020080000800002001600008000080041800411180201100991001008000080000010080000008001000138001361131700511041603280038080000008000080000801008004280042800428004280042
16020480174621000001120000800261661825240100801008001580000801008000080000435899037588244924001080022080041800415992435999924010020080000800002001600008000080041800411180201100991001008000080000110080000008001200158000001131700511041603380038080000998000080000801008004280042800428004280042
1602048017562000000019000080026006682524011980100800198000080100800008000043589863758824491867708002208004180041599243599992405142008000080000200160000800008004180041118020110099100100800008000011008000001480000001580013000000512931603480038080000098000080000801008004280042800428004280042
1602048004162100000013200008002616002524011680100800168000080100800008000043590023758824491867708002208004180041599243599992401002008000080000200160000800008004180041118020110099100100800008000001008000001480000001380013610000511031604380038080000008000080000801008017680042800428004280042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f2223243f4346494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)rob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600258004162100010000190000800261665762240028800108001980000800108000080000435841737588244918542082552800418004159946036002124001020800008000020160000801448017680041118002110910108000080000010800000148001300128010300121750200516161480038180000968000080000800108004280042800428004280042
160024800416200000000027000080026166482524002980105800198000080010800008000043584093758824491854208002280041800415994602260021240010208014080000201600008000080041800411180021109101080000800000108000000800120011788001360101750200131613580038180000968000080000800108004280042800428004280042
160024800416200010000015088000800261664252400288001080015800008001080000800004358417375882449185350800228004180041599460360021240010208000080000201600008000080041800411180021109101080000800000108000001480009001580101611017502001016141380038180000068000080000800108004280042800428017380042
16002480041620000000003100008002616652524003180010800188000080010801408000043584333758824491838308002280041800415994603600212400102080000800002016000080000800418004111800211091010800008000001080000014800131016800136113050410616141380038180000968000080000800108004280042800428004280042
160024800416200000001019000080026166825240029800108001980000800108000080136435841737588244918531080044800418017459946036002124001020800008000020160000800008004180041118002110910108000080000010800000148010400158001361111750200916136800380800001168000080000800108004280042800428004280042
16002480041620000010201988100800261665025240028800108001880000800108000080000435842937588244918536080022800418004159946036002124001020801548000022160000800008004180041118002110910108000080000010800000148001200382319611014502001316111380038180000968000080000800108004280042800428004280042
1600248004162000000000198800080026166625240029800108000080000800108000080000435840937588244924222080044800418004159946036002124001020800008000020160000800008004180041118002110910108000080000010800000148010200168001361101750200616141380158180093998000080000800108004280042800428004280042
1600248017562100000000120000800261665252400298001080019800008001080000801374358421375882449183830800228004180173599460360021240010208000080000201600008000080041800411180021109101080000800000108000001480013001380012611017502001341141380038180000998000080000800108017580042800428004280042
16002480041620000000002788000800261665025240029800108001880000800108000080000435842537588244918536080022800418004159946036002124001020801448000020160000800008004180041118002110910108000080000010800000148001300128001361100502001416141480038180000908000080000800108004280042800428004280042
1600248004162200000000200000800261666252400108001080108800008001080000800004358417375882449185920800228004180041599460360021240010208000080000201600008000080041801731180021109101080000800001108000001480102001380012611014502001316121380038180000978000080000800108004280042801758004280042