Firestorm: LD1R (post-index, 8H) measurements

Code:

  ld1r { v0.8h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.003

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.003

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5e	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
62005	29080	233	1	24	1	1	27	1	1	1	0	0	1	0	1	0	0	4707	28578	0	0	16945	3004	1000	1004	1000	1000	1000	1000	5000	5000	11910	0	12	0	0	22599	28880	29008	3	29	3000	1000	1000	2000	1000	28818	28930	1	1	61001	1000	1000	0	1002	1	3	1006	0	0	3	6	1000	3	1	3	1	3	0	13079	9356	6899	3148	16	67	20313	3239	3819	25	66	69	28436	1000	15733	12606	13988	1000	1000	1000	29107	29111	28980	29010	29069
62004	29167	233	1	28	1	1	33	1	1	1	0	0	13	0	1	0	0	4643	28492	0	0	16999	3001	1000	1006	1000	1000	1000	1000	5000	5001	11937	0	10	0	0	22588	28841	28959	3	10	3000	1000	1000	2000	1000	28877	28996	1	1	61001	1000	1000	0	1001	2	2	1002	0	0	1	1	1001	2	1	2	1	1	0	13162	9352	6791	3102	14	67	20320	3223	3815	21	61	67	28388	1000	15567	12846	14012	1000	1000	1000	28972	29041	29043	29085	29032
62004	28887	232	1	29	0	0	24	1	0	0	0	0	4	0	0	0	0	4696	28590	0	0	17120	3006	1000	1001	1000	1000	1000	1000	5000	5000	11931	0	0	0	8	22631	28932	29052	3	10	3000	1000	1000	2000	1000	28955	28971	1	1	61001	1000	1000	0	1001	2	2	1001	0	1	2	4	1000	2	1	3	1	1	0	13152	9197	6829	3089	12	65	20475	3261	3809	12	62	64	28438	1000	15934	12973	14064	1000	1000	1000	29090	28970	29025	28952	29068
62004	29054	233	1	23	1	1	31	1	0	0	0	0	16	0	0	0	0	4663	28670	0	0	17167	3001	1000	1001	1000	1000	1000	1000	5000	5000	11904	0	8	0	0	22596	28861	28991	3	10	3000	1000	1000	2000	1000	29012	28997	1	1	61001	1000	1000	1	1002	2	2	1003	0	1	1	4	1000	2	1	0	1	1	0	13033	9406	6893	3099	17	64	20600	3284	3809	21	61	59	28451	1000	15529	12995	14177	1000	1000	1000	29081	29048	29170	29137	29074
62004	29158	233	1	22	1	1	21	1	0	0	0	0	3	0	1	0	0	4590	28519	0	0	17075	3003	1000	1001	1000	1000	1000	1000	5000	5000	11911	2	4	0	0	22632	28828	29121	3	10	3000	1000	1000	2000	1000	28913	28990	2	1	61001	1000	1000	0	1002	1	3	1005	0	0	0	1191	1000	0	2	2	1	0	250	13203	9216	6924	3130	14	60	20497	3204	3810	23	67	69	28472	1001	15662	12700	14095	1000	1000	1000	29169	29140	29261	29080	29098
62004	29068	234	1	32	2	1	27	2	0	0	1	3	135	88	1	0	0	4633	28843	0	0	17052	3004	1000	1005	1000	1000	1000	1000	5000	5000	11937	0	4	1	9	22628	29035	29210	6	28	3000	1001	1001	2004	1000	28954	29121	3	1	61001	1000	1000	0	1013	7	3	1003	0	0	3	1	1000	0	2	0	1	11	0	13143	9360	6871	3127	13	64	20411	3226	3814	20	67	61	28449	1000	15915	12818	14370	1000	1000	1000	29270	29301	29355	29228	29302
62004	29100	233	1	31	2	2	26	2	0	0	0	0	6	0	0	0	1	4699	28729	0	0	17266	3001	1000	1001	1000	1000	1000	1000	5000	5000	12244	0	4	0	0	22640	28685	28836	3	10	3000	1000	1000	2000	1000	28841	28964	1	1	61001	1000	1000	0	1003	3	0	1002	0	1	1	1	1001	0	1	3	1	1	0	12923	9434	6968	3182	13	64	20250	3187	3814	24	65	60	28279	1000	15971	12719	14048	1000	1000	1000	28927	28936	28846	28887	28940
62004	28963	233	1	28	0	0	33	1	0	0	0	0	13	0	0	0	0	4752	28674	0	0	16932	3001	1000	1001	1000	1000	1000	1000	5000	5000	11902	0	5	1	8	22583	28855	29056	3	10	3000	1001	1000	2000	1000	28881	28785	1	1	61001	1000	1000	0	1002	1	0	1004	0	3	1	4	1000	0	1	2	1	1	251	12997	9203	6810	3079	14	65	20752	3252	3816	16	59	61	28406	1000	15534	12657	14285	1000	1000	1000	28854	28809	28796	28807	28822
62004	28883	234	1	25	0	1	27	0	0	0	0	0	15	0	0	0	0	4689	28379	0	0	16857	3003	1000	1003	1001	1000	1000	1000	5000	5000	11906	0	0	0	8	22655	28816	28972	3	29	3000	1000	1000	2000	1000	28836	28758	1	1	61001	1000	1000	0	1002	2	2	1002	0	0	1	4	1000	0	1	2	1	3	0	13039	9305	6842	3210	14	63	20258	3287	3807	26	60	65	28305	1000	15805	12619	13684	1000	1000	1000	28899	28940	28961	28788	28942
62004	28886	223	1	29	1	1	25	1	0	0	0	0	1	0	0	0	1	4686	28535	0	0	16824	3003	1000	1003	1000	1000	1000	1000	5000	5000	11938	0	9	0	0	22565	28696	29002	3	10	3000	1000	1000	2000	1000	28787	28840	1	1	61001	1000	1000	0	1001	2	2	1002	0	0	1	2	1000	0	1	0	1	1	0	13248	9487	6886	3138	20	71	20346	3195	3817	19	65	69	28349	1000	15603	12770	14125	1000	1000	1000	28946	28871	28887	28786	28884

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1r { v0.8h }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0056

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	aa	ac	af	b5	bb	bc	l1d cache miss ld nonspec (bf)	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60205	140053	1049	1	1	0	0	0	0	0	0	14	0	0	0	140043	139577	25	80118	50100	20004	10000	40100	20000	10000	1247689	5304601	10710678	0	140032	0	140056	140056	132438	14	132434	70100	30200	10000	20082	60200	20000	20000	140056	140137	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	2	1	10002	1	1	0	3196	10000	1	1	0	1	0	1	0	0	0	0	3210	0	1	93	1	1	139713	50000	6	6	9	10000	10000	50100	140150	140057	140057	140055	140042
60204	140056	1085	1	1	1	0	0	0	0	0	2	0	0	0	140045	139577	25	80104	50100	20004	10001	40100	20000	10000	1245664	5304715	10710678	1	140029	0	140056	140056	131970	3	132422	70100	30200	10000	20083	60200	20000	20000	140056	140053	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	1	10002	1	0	0	4	10000	1	1	0	1	0	1	0	0	0	0	3210	0	1	93	1	1	139787	50000	0	0	9	10000	10000	50100	140057	140055	140055	140057	140132
60204	140056	1125	1	0	1	0	0	0	0	0	1	0	0	1	140038	139587	25	80104	50100	20004	10001	40100	20000	10000	1247785	5304487	10710678	0	140031	0	140053	140058	131970	3	132437	70100	30445	10121	20000	60200	20080	20080	140047	140054	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	1	10001	1	0	0	1	10000	0	1	0	1	0	0	1	0	0	0	3210	0	1	170	1	1	139720	50000	6	7	10	10000	10000	50100	140057	140055	140054	140057	140057
60204	140053	1126	1	1	1	0	0	0	0	0	2	0	0	1	140049	139577	25	80104	50100	20004	10000	40100	20000	10000	1245691	5308580	10710678	0	140029	0	140041	140053	131967	3	132492	70100	30200	10000	20000	60200	20000	20000	140056	140053	2	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10000	0	0	0	0	10000	1	1	0	1	0	1	0	0	0	0	3210	0	1	93	1	1	139722	50000	9	9	6	10000	10000	50100	140061	140057	140153	140054	140057
60204	140057	1125	1	0	1	1	0	0	0	0	1	0	0	0	140132	139617	25	80102	50100	20004	10000	40100	20000	10000	1245682	5304715	10710756	0	140029	0	140056	140056	131970	3	132431	70100	30200	10000	20000	60200	20000	20000	140056	140053	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10001	1	0	0	4	10000	1	1	0	1	0	1	1	0	0	0	3210	0	2	93	1	2	139711	50000	6	6	9	10000	10000	50100	140042	140056	140057	140055	140057
60204	140047	1124	1	0	0	0	0	0	0	0	2	0	0	0	140041	139579	25	80104	50100	20004	10000	40100	20000	10000	1245673	5304601	10710678	0	140023	0	140053	140053	131967	3	132422	70100	30200	10000	20000	60200	20000	20000	140056	140047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	2	1	10002	0	1	0	1	10000	1	1	0	1	0	1	0	0	0	0	3210	0	1	93	2	1	139719	50000	0	0	7	10000	10000	50100	140057	140057	140057	140054	140054
60204	140053	1125	1	0	0	2	0	0	1	1	1	0	0	0	140041	139671	25	80118	50100	20004	10000	40100	20000	10000	1245664	5304793	10710678	0	140030	0	140056	140150	131970	3	132437	70361	30322	10000	20000	60200	20000	20000	140041	140056	1	1	50201	100	99	100	40100	10000	10000	0	100	10005	1	1	10001	0	1	0	1	10000	1	1	0	1	0	1	1	0	0	0	3210	0	1	93	1	1	139720	50000	6	0	9	10000	10000	50100	140042	140059	140051	140057	140144
60204	140056	1125	1	0	0	0	0	0	0	2	2	0	0	0	140035	139577	51	80102	50100	20004	10000	40100	20000	10000	1245646	5304715	10710678	0	140109	0	140056	140145	131968	3	132437	70100	30324	10000	20000	60200	20000	20000	140056	140053	1	1	50202	100	99	100	40100	10000	10000	0	100	10001	0	0	10001	1	0	0	1	10000	1	1	0	1	0	0	3	0	0	0	3210	0	1	93	1	2	139713	50000	6	6	9	10000	10000	50100	140057	140053	140057	140057	140042
60204	140059	1125	1	0	0	0	0	0	0	0	2	0	0	0	140038	139577	25	80102	50100	20004	10000	40100	20000	10000	1246255	5304715	10710678	0	140023	0	140054	140056	131970	3	132435	70100	30200	10000	20000	60200	20000	20083	140056	140053	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	1	10002	0	3	0	0	10000	1	1	0	0	0	1	0	0	0	0	3234	1	1	93	1	1	139717	50000	6	6	9	10000	10000	50100	140057	140057	140054	140142	140057
60204	140054	1125	1	1	2	0	0	0	0	0	14	0	0	0	140038	139574	25	80102	50100	20002	10000	40401	20000	10000	1245303	5309876	10710210	0	140169	0	140147	140126	131970	13	132589	70883	31432	10080	20320	60678	20160	20245	140407	140244	4	1	50201	100	99	100	40100	10000	10000	0	100	10004	4	1	10004	0	3	0	12786	10002	1	1	0	1	0	1	0	0	0	0	3280	0	1	131	2	2	141965	50020	7	6	9	10000	10000	50100	140236	140339	140323	140333	140328

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0056

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60025	140054	1049	1	0	1	0	0	0	0	0	0	0	14	0	0	0	140041	139660	25	80014	50010	20004	10000	40010	20000	10000	1245815	5307849	10717811	0	1	140032	140056	140056	132004	3	132464	70010	30020	10000	20000	60020	20080	20000	140056	140053	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	1	1	10002	0	8	0	19	10000	1	1	1	1	1	0	3140	5	88	5	4	139727	50000	9	6	9	10000	10000	50010	140057	140057	140057	140057	140061
60024	140056	1086	1	0	0	0	0	0	0	0	0	0	11	0	0	0	140041	139660	25	80014	50010	20004	10000	40010	20000	10000	1245842	5307732	10717577	0	1	140026	140056	140056	132004	3	132464	70308	30020	10000	20000	60020	20000	20000	140056	140053	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	1	10002	0	6	0	1	10000	1	1	1	1	0	0	3140	3	88	4	4	139727	50000	9	6	9	10000	10000	50010	140057	140057	140054	140054	140058
60024	140056	1085	1	0	0	1	0	1	0	0	0	0	2	0	0	0	140041	139659	25	80014	50010	20004	10000	40010	20000	10000	1245842	5307732	10717454	0	0	140030	140057	140054	132004	3	132461	70010	30020	10000	20000	60020	20000	20000	140056	140053	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	1	10001	0	39	0	1	10000	1	1	1	1	2	0	3140	3	88	5	4	139727	50000	9	9	9	10000	10000	50010	140057	140057	140057	140057	140054
60024	140056	1086	1	0	0	0	0	0	0	0	0	0	23	0	0	0	140125	139735	25	80014	50010	20004	10000	40010	20000	10000	1245842	5307732	10720990	0	1	140032	140041	140041	132005	3	132464	70010	30020	10000	20000	60020	20000	20000	140041	140041	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10001	0	9	1	1	10000	0	1	1	1	0	0	3140	3	88	5	5	139727	50000	9	6	0	10000	10000	50010	140057	140042	140042	140058	140061
60024	140053	1086	1	0	0	1	0	0	0	0	0	1	1	0	0	0	140026	139660	25	80014	50050	20007	10000	40010	20000	10000	1245842	5307504	10717577	1	0	140017	140056	140055	132011	3	132461	70010	30020	10000	20000	60262	20000	20000	140056	140056	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	1	10001	0	9	1	1	10000	1	1	1	1	1	0	3140	5	106	4	4	139727	50000	9	9	9	10000	10000	50010	140057	140051	140042	140057	140079
60024	140056	1085	1	0	0	1	0	0	0	0	0	0	2	0	0	0	140035	139657	25	80014	50010	20004	10000	40010	20000	10000	1245815	5307732	10717577	0	1	140032	140056	140056	132004	3	132464	70010	30020	10000	20000	60020	20000	20000	140041	140053	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	1	1	10002	0	51	0	1	10000	1	1	1	1	1	0	3140	5	88	4	4	139727	50000	0	6	9	10000	10000	50010	140057	140059	140058	140042	140098
60024	140056	1085	1	0	0	0	0	0	0	0	0	0	29	0	0	0	140026	139645	25	80014	50010	20004	10000	40161	20094	10000	1245821	5307110	10717890	0	1	140029	140143	140056	132004	3	132466	70010	30141	10000	20000	60020	20000	20000	140056	140056	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	1	1	10001	0	82	0	4	10000	1	1	1	1	1	0	3140	4	88	5	5	139729	50000	9	6	0	10000	10000	50010	140042	140052	140058	140057	140087
60024	140056	1086	1	0	0	0	0	1	0	0	0	0	2	0	0	0	140026	139645	25	80014	50010	20004	10001	40010	20000	10000	1245842	5307110	10717454	0	1	140032	140056	140053	132004	3	132464	70010	30020	10000	20000	60020	20000	20080	140056	140042	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	1	1	10003	0	51	0	1	10000	0	1	1	1	0	0	3140	5	88	4	5	139712	50000	6	6	0	10000	10000	50010	140054	140042	140057	140054	140068
60024	140144	1085	1	0	1	1	0	1	0	1	0	0	2	0	0	0	140026	139647	25	80014	50010	20004	10000	40010	20000	10040	1245842	5307732	10717577	0	1	140032	140053	140053	132004	13	132464	70010	30020	10000	20000	60020	20000	20000	140041	140139	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	0	10001	0	7	0	1	10001	0	1	0	1	0	0	3140	3	88	5	4	139727	50000	6	0	6	10000	10000	50010	140057	140057	140153	140057	140064
60024	140041	1085	1	0	0	0	0	0	0	0	0	0	1	0	0	0	140119	139635	25	80014	50050	20004	10000	40010	20000	10000	1245842	5307732	10721342	0	1	140188	140057	140056	132005	3	132464	70271	30020	10000	20000	60020	20000	20000	140056	140056	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	1	1	10001	0	11	1	1	10000	1	1	1	1	0	0	3168	3	112	4	5	139884	50214	11	6	9	10000	10000	50010	140242	140328	140314	140238	140400

Test 3: throughput

Count: 8

Code:

  ld1r { v0.8h }, [x6], x8
  ld1r { v0.8h }, [x6], x8
  ld1r { v0.8h }, [x6], x8
  ld1r { v0.8h }, [x6], x8
  ld1r { v0.8h }, [x6], x8
  ld1r { v0.8h }, [x6], x8
  ld1r { v0.8h }, [x6], x8
  ld1r { v0.8h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	7b	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch call (8e)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160205	80041	642	1	0	1	0	0	0	0	0	0	32	0	0	0	80026	1	6	6	14	25	240131	80100	80032	80000	80100	80000	80000	4359002	3758824	4918898	0	80022	80041	80041	59924	3	59999	240524	0	200	80000	80000	200	160000	80000	80041	80041	1	1	80201	100	0	99	100	100	80000	80000	100	80007	7	23	80113	1	1	27	80019	6	1	25	23	7	0	0	5110	1	16	1	1	80038	0	80095	9	6	80000	80000	80100	80042	80042	80042	80042	80042
160204	80041	643	1	0	0	0	0	0	0	0	0	32	0	0	0	80026	1	6	6	8	25	240119	80100	80031	80000	80100	80000	80000	4358982	3762988	4918677	0	80022	80041	80041	59924	3	59999	240100	0	200	80000	80000	200	160000	80000	80041	80041	1	1	80201	100	0	99	100	100	80000	80000	100	80007	0	23	80026	0	0	9	80019	6	1	26	17	6	0	0	5110	1	16	1	1	80146	1	80000	9	10	80000	80000	80100	80042	80042	80176	80042	80042
160204	80041	643	1	0	1	0	0	0	0	0	0	18	0	0	0	80026	1	6	6	5	25	240119	80100	80019	80000	80100	80000	80000	4359006	3758824	4918893	0	80022	80041	80041	59924	3	59999	240100	0	200	80000	80000	200	160000	80000	80041	80041	1	1	80201	100	0	99	100	100	80000	80000	100	80007	7	23	80015	0	1	12	80019	6	1	13	23	7	0	0	5110	1	16	1	1	80038	1	80000	10	9	80000	80000	80100	80042	80042	80042	80042	80042
160204	80041	643	1	0	1	0	1	0	0	0	0	31	0	1	0	80026	1	6	6	8	25	240132	80100	80021	80000	80100	80000	80000	4358986	3758824	4918985	0	80022	80041	80041	59924	22	59999	240100	0	200	80000	80000	200	160000	80000	80041	80041	1	1	80201	100	0	99	100	100	80000	80000	100	80007	6	23	80026	0	0	26	80019	6	1	25	23	7	1	0	5110	1	16	1	1	80038	1	80000	9	6	80000	80000	80100	80042	80042	80042	80176	80042
160204	80041	643	1	0	0	0	1	0	0	0	0	32	0	1	0	80026	1	6	6	8	25	240405	80100	80019	80000	80100	80000	80000	4358986	3758823	4918896	0	80126	80041	80041	59924	3	59999	240100	0	200	80000	80143	200	160000	80000	80041	80041	1	1	80201	100	0	99	100	100	80000	80000	100	80006	6	23	80025	0	0	25	80018	6	1	26	23	7	1	0	5110	1	16	1	1	80038	1	80000	9	9	80000	80000	80100	80042	80042	80042	80175	80042
160204	80041	643	1	0	1	0	1	0	0	0	0	31	0	1	0	80026	1	6	6	10	25	240403	80100	80031	80000	80100	80000	80000	4358982	3758823	4918896	0	80125	80041	80041	59924	3	59999	240100	0	200	80000	80000	200	160000	80000	80041	80041	1	1	80201	100	0	99	100	100	80000	80000	100	80007	7	14	80027	0	0	26	80019	6	1	25	17	7	0	0	5110	1	16	1	1	80038	1	80000	9	9	80000	80000	80100	80042	80042	80042	80042	80042
160204	80041	643	0	0	1	0	1	0	0	0	0	44	0	1	0	80026	1	6	6	12	25	240404	80100	80031	80000	80100	80000	80000	4358986	3758825	4918896	0	80129	80041	80041	59924	3	59999	240100	0	200	80000	80000	200	160000	80000	80041	80041	1	1	80201	100	0	99	100	100	80000	80000	100	80006	6	23	80026	1	1	33	80019	6	1	10	23	0	0	0	5110	1	16	1	1	80038	1	80000	9	13	80000	80000	80100	80042	80042	80042	80042	80042
160204	80041	642	1	0	0	0	1	1	1	0	0	16	0	1	1	80026	1	6	6	8	25	240132	80100	80031	80000	80100	80000	80000	4358986	3758824	4918904	1	80022	80161	80041	59924	3	59999	240100	0	200	80000	80000	200	160000	80000	80041	80041	1	1	80201	100	0	99	100	100	80000	80000	100	80099	8	23	80027	0	0	12	80019	6	1	10	17	0	1	0	5110	1	16	1	1	80038	0	80000	9	9	80000	80000	80100	80042	80042	80042	80042	80042
160204	80041	643	0	0	0	0	1	0	0	0	0	42	0	1	1	80026	1	6	6	8	25	240131	80100	80019	80000	80100	80000	80000	4358982	3758823	4918898	1	80022	80041	80041	59924	3	59999	240100	0	200	80143	80000	200	160000	80000	80041	80041	1	1	80201	100	0	99	100	100	80000	80000	100	80008	8	23	80027	0	3	28	80019	6	1	6	23	7	0	0	5110	3	16	1	1	80038	0	80000	9	9	80000	80000	80100	80042	80042	80042	80042	80042
160204	80175	643	1	0	1	0	1	0	0	0	0	32	0	1	0	80026	1	6	6	8	25	240131	80100	80031	80000	80100	80000	80000	4358986	3758824	4918893	0	80022	80041	80041	59924	3	59999	240100	0	200	80000	80000	200	160000	80000	80041	80041	1	1	80201	100	0	99	100	100	80000	80000	100	80006	7	23	80025	0	1	25	80019	6	1	25	23	7	0	0	5131	1	34	1	1	80144	1	80092	6	6	80000	80000	80100	80176	80306	80311	80174	80177

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	df	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160025	80041	643	1	1	0	0	0	0	0	0	34	0	0	0	1	80026	0	6	6	9	25	240017	80010	80031	80000	80010	80000	80000	4358433	3758824	4918758	1	80022	80041	80041	59946	0	3	60021	240010	20	80000	80000	20	160000	80000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	0	10	80006	7	23	0	80006	0	0	0	25	80019	6	1	25	23	7	1	0	0	5023	3	16	4	4	3	80038	0	80000	9	0	80000	80000	80010	80042	80042	80042	80042	80042
160024	80041	643	1	0	0	1	1	1	0	0	9	0	1	0	0	80026	1	0	0	8	25	240017	80010	80032	80000	80010	80000	80000	4358393	3758824	4918421	0	80022	80041	80041	59946	0	3	60021	240010	20	80000	80000	20	160000	80000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	0	10	80006	7	23	0	80026	0	0	0	27	80019	6	1	25	23	7	0	0	0	5023	4	16	3	4	3	80038	0	80000	9	0	80000	80000	80010	80042	80042	80042	80042	80042
160024	80041	643	1	1	0	1	0	0	2	0	37	0	1	0	0	80026	1	6	0	13	25	240017	80010	80032	80000	80010	80000	80000	4358393	3758823	4918766	1	80022	80041	80041	59946	0	3	60021	240010	20	80000	80000	20	160000	80000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	0	10	80007	7	23	0	80007	0	0	0	7	80019	6	1	25	0	7	0	0	0	5023	3	16	4	2	3	80038	1	80000	9	0	80000	80000	80010	80042	80042	80042	80042	80042
160024	80041	643	1	0	0	0	0	0	0	0	9	0	1	0	0	80026	0	6	6	1	25	240041	80010	80032	80000	80010	80000	80000	4358397	3758823	4918761	0	80022	80041	80041	59946	0	3	60021	240010	20	80000	80000	20	160000	80000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	0	10	80007	8	0	0	80025	0	1	0	25	80019	6	1	25	23	7	0	0	0	5023	5	16	3	4	3	80038	0	80000	9	9	80000	80000	80010	80042	80042	80042	80042	80042
160024	80041	643	1	1	0	0	0	0	0	0	34	0	1	0	1	80026	1	6	6	14	25	240016	80010	80032	80000	80010	80000	80000	4358401	3758822	4918424	0	80022	80041	80041	59946	0	3	60021	240010	20	80000	80000	20	160000	80000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	0	10	80006	8	0	0	80025	0	1	1	25	80018	6	0	6	23	7	0	0	0	5023	3	16	4	3	3	80038	1	80000	12	9	80000	80000	80010	80042	80042	80042	80042	80042
160024	80041	643	1	0	0	1	0	0	0	0	7	0	0	0	0	80026	1	0	0	10	25	240017	80010	80031	80000	80010	80000	80000	4358425	3758824	4918413	0	80022	80041	80041	59946	0	3	60021	240010	20	80000	80000	20	160288	80000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	0	10	80094	7	23	0	80007	0	0	1	25	80194	6	1	25	23	7	0	0	0	5023	4	16	3	4	3	80038	0	80000	0	0	80000	80000	80010	80042	80042	80042	80042	80042
160024	80041	643	1	0	0	0	1	1	0	0	167	0	1	0	0	80026	0	0	0	8	25	240016	80010	80007	80000	80010	80000	80000	4358389	3758825	4918761	0	80022	80041	80041	59946	0	3	60021	240010	20	80144	80000	20	160000	80000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	1	10	80008	7	26	0	80026	0	0	0	7	80019	6	1	26	23	6	0	0	0	5023	3	16	3	3	3	80038	1	80000	0	9	80000	80000	80010	80042	80042	80042	80042	80042
160024	80041	643	1	1	0	0	0	0	0	0	35	0	1	0	0	80026	1	6	6	3	25	240042	80010	80031	80000	80010	80000	80000	4361827	3758824	4918761	0	80022	80041	80041	59946	0	3	60021	240010	20	80000	80000	20	160000	80000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	0	10	80006	7	23	0	80025	0	0	0	24	80019	6	1	25	0	6	0	0	0	5023	3	16	4	2	3	80038	1	80000	9	9	80000	80000	80010	80042	80042	80042	80042	80042
160024	80041	642	1	0	0	0	0	0	0	0	55	0	1	0	0	80026	1	6	6	10	25	240311	80010	80032	80000	80010	80000	80000	4358401	3758824	4918758	0	80022	80041	80041	59946	0	3	60021	240010	20	80000	80000	20	160000	80000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	0	10	80008	7	23	0	80008	0	1	1	26	80106	6	0	26	23	6	0	0	0	5023	2	16	3	3	3	80038	1	80000	9	0	80000	80000	80010	80042	80042	80042	80042	80042
160024	80041	642	1	1	0	1	0	1	0	0	35	0	1	0	1	80026	0	6	6	10	25	240041	80010	80031	80000	80010	80000	80000	4358401	3758824	4918759	0	80022	80041	80041	59946	0	3	60021	240010	20	80000	80000	20	160000	80000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	0	10	80008	7	23	0	80025	0	0	0	25	80018	6	1	26	23	6	1	0	0	5023	3	16	4	3	3	80038	0	80000	9	0	80000	80000	80010	80042	80042	80042	80042	80042

LD1R (post-index, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations