Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, 2 regs, 1D)

Test 1: uops

Code:

  ld1 { v0.1d, v1.1d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f18191e1f2223243a3f43464951schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)5f6061696b6d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst simd load (98)inst ldst (9b)9dl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)c2cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaebec? ldst retires (ed)? simd retires (ee)f5f6f7f8fd
6200528531225119119000005901005030280900002329510001000100050004181607202804328232310100020001000282842863311610011000100001000021001000010002020139291003871983398885197443090382311595827940146041232214690100010002871428267283652833328707
62004283482121130180000015010051872814400023336100010001000500021816060028080283313101000200010002857528287116100110001000010000010010000100011201373310183720431241064196703410382116586327892145701250513929100010002826128293282902837328326
6200428285211124016000002001005138280770012346010001000100050005101606802797528210310100020001000286732843711610011000100001000021001000010011120138191011771733341959201213372382012656427492147461241814075100010002833228266282942828328297
62004283702130150190000032400005024280900102333710001000100050000001606202837828286310100020001000282342825511610011000100001000021000000010001020131541015769493336758197643346381513595627890147081238213699100010002881328425286742827028297
62004282782130200220000017010049762807300023309100010001000500020016077028036283283101000200010002823428708116100110001000110000210000004100121201377010251719234481067197293289381513606027922144141222713974100010002834328344283732826028334
62004283092120160200000020010050312804501023438100010001000500001016068027995282753101000200010002820528314116100110001000010000210010101100120201389510060716531571064197043272381512646128191144921315014598100010002839128326282892824028405
62004283152122130190000041901004975280560002336410001000100050000101607002808528431310100020001000286242855311610011000100001000021000000110001120136861022071883467757196993137381917626127894154741225013682100010002831828272287102847328749
620042835821501801800000180100477228036011237351000100010005000018160720280412824831010002000100028146286551161001100010000100002100101001000012013582939671863316662196133135382212625727946143971246813786100010002832828247282492829428430
620042877021201701600000210100517628135011233191000100010005000000160530279902826231010002000100028248283011161001100010000100002100000011001202013053931969323158966198503215381914545927973152671329514684100010002842728295284482830128409
620042881423601701901000150000507328030001232101000100010005000200160510280872866031010002000100028157283661161001100010000100002100101011001002013689992572573389759197043116381611615927899146881251113658100010002827528789282882827228326

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.1d, v1.1d }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0054

retire uop (01)cycle (02)03mmu table walk data (08)0e0f18191e1f22233a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5l1d cache miss ld nonspec (bf)c2branch mispred nonspec (cb)cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
602051200578990100010000120048119503109459256010340100100011000030100100001000010795525735293611828513120027120051120054111896311240750100302002000010000602001000010000120035120035115020110099100401001000010000110010000011000002001000010003210311108111196494000210109100001000040100120055120055120052120036120036
602041200518990010010000120022119509109461256010340102100011000030100100001000010808965739062611828513120030120054120054111900311241950100302002000010000602001000010000120035120051115020110099100401001000010000110010000011000000001000011003210314152111196464000213109100001000040100120517120719120400120765120575
602041200548991001317303922880001218371208151101976876043640327100521004232233107851024910793965735293611901603120030120054120059111896311241250100302002000010000602001000010000120054120035115020110099100401001000010000010010000011000000001000111003210001121111196664000210109100001000040100120036120036120036120055120055
6020412005489900000100001200591195091094492560103401021000110000301001000010000107912657362306118285031200301200351200541118963112407501003020020000100006020010064100001200541200511150201100991004010010000100000100100000010000000010000110032100011211111964640002101012100001000040100120055120036120055120060120055
602041200548990000000000120056119509109461256010040102100001000030100100001000010791265736230611759903120030120054120054111900311240750100303912000010000602001000010000120054120051115020110099100401001000010000110010000011000000001000011003210311108111196564000210109100001000040100120055120055120052120055120036
602041200548990000010000120072119495109459256010340102100011000030100100001000010795525735293611828510120027120054120035111881311240750100302002000010000602001000010000120057120051115020110099100401001000010000110010000011000000001000011003210311121111196464000213109100001000040100120055120036120055120055120036
60204120054899000001010012009211950310946125601034010210001100003010010000100001079423573623061175991012003012005412005411190031124075010030200200001000060200100001000012005412003511502011009910040100100001000011001000001100000000100011000321031113511119646400371309100001000040100120055120055120055120060120055
6020412005489900000001001200391195091094612560103401001000110000301001000010000107912657362306119016031200301200351200351118963112407501003020020000100006020010000100001200351200511150201100991004010010000100000100100000110000000010000100032103111211111966640002101312100001000040100120036120052120052120055120055
602041200548990100000100120054119509109461256010340102100011000030100100001000010793965736230611901603120027120063120054111900311240750100302002000010000602001000010000120054120051115020110099100401001000010000110010000011000000001000010003210311121111196564000210100100001000040100120052120052120055120036120036
6020412003589901100000001200801195031094612560100401021000010000301001000010000107939657352936118285031200111200511200541118963112417501003020020000100006020010000100001200541200351150201100991004010010000100001100100000110000000310000110032103111211111964640002131012100001000040100120055120036120036120036120055

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0050

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f18191e1f2223243a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)int prf full (71)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5l1d cache miss ld nonspec (bf)c2branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
6002512005489900001000100000120020119480109455256001340010100011000030010100001000010798455735293612558101200261200471200501119180311244750010300202000010000600201000010000120050120047115002110910400101000010000010100002110000000100001100031402995311966540000900100001000040010120036120036120051120051120051
6002412003589900000000000000120035119481109458256001340012100011000030010100001000010797695735888612558111200261200471200501119150311244750010300202000010000600201000010000120050120047115002110910400101000010000110100000010000000100011100031405993511966540002660100001000040010120051120036120051120036120036
6002412005089900000000100000120035119483109455256001340012100011000030010100001000010798455735293612434401200261200351200471119950311244750010300202000010000600201000010000120035120047115002110910400101000010000010100000110000000100000100031403995311967040002668100001000040010120036120051120036120036120037
60024120050899000000001010001200201198001094582560013400101000110000300101000010000107980957366476125581112001112003612003511200203112437500103002020000100006002010000100001200351200471150021109104001010000100000101000001100000014364100001100031404943311965040002668100001000040010120051120036120051120036120051
6002412005089900000000000000120020119489109443256001340010100001000030159100001000010797695736035612571411200111200471200501119180311244750010300202000010000600201000010000120050120037115002110910400101000010000010100000110000000100000100031403995311966540002090100001000040010120036120051120051120036120036
6002412005090000000000000000120035119483109443256001340018100011000030010100001000010797695735293612571401200111200501200471119030311243750010300202000010000600201000010000120050120047115002110910400101000010000010100000110000000100001000031404994311966840002965100001000040010120051120051120051120036120051
6002412003589900000000100000120035119489109495256001340012100011000030010100001000010798455736035612434411200231200501200351119150311244750010300202000010000600201000010000120035120035115002110910400101000010000010100000110000000100001100031404944311966840002990100001000040010120051120036120036120036120422
6002412005089910001100100000120035119480109458256001040012100011000030010100001000010798095735293612571411200231200351200501119150311244750010300202000010000600201000010000120035120047115002110910400101000010000010100000010000200100000100031407994311965040000068100001000040010120054120051120418120037120051
60024120159899000000692201000120020119489109458256001040010100011000030010100001000010798455736035612571401200231200501200351119030311243750010300202000010000600201000010000120035120035115002110910400101000010000010100000110000000100001100031403942411965040000090100001000040010120036120048120051120036120051
6002412005089900001102100000120020119483109455256001340044100011000030010100001000010797695736035612571411200261200501200521120130311243750010300202000010000600201000010000120050120444615002110910400101000010000110100000110000000100011100031405993511966540002905100001000040010120051120051120048120051120036

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.1d, v1.1d }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

retire uop (01)cycle (02)03l2 tlb miss data (0b)0e0f181e1f22233a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)int prf full (71)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5l1d cache miss ld nonspec (bf)c2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
60205120051899000010100120036119495109459256010340102100001000030100100001000010795525736084611828501200111200521200511118960311241850100302002000010000602001000010000120051120051115020110099100401001000010000010010000001000000010000110032102108221196564000210100100001000040100120052120036120052120052120052
60204120051928000010100120036119495109459256010340102100001000030100100001000010795525736084611828501200111200511200511118960311241750100302002000010000602001000010000120051120051115020110099100401001000010000010010000011000000310000110032102127221199734000210109100001000040100120052120052120052120052120052
602041200358990000101001200361195031094592560103401021000110000301001000010000107955257360846118285012002712005112005111189603112417501003020020000100006020010000100001200511200511150201100991004010010000100000100100000110000660010000110032102135221196564000210109100001000040100120052120052120052120036120052
60204120035899000010100120036119495109459256010040102100011000030100100001000010795525735293611759901200111200541200351118960311241750100302002000010000602001000010000120051120051115020110099100401001000010000010010000011000015001000001003210210822119656400020109100001000040100120036120052120052120036120052
60204120051899000010100120036119496109443256010340102100011000030100100001000010791265736180611760711200111200511200511118960311241750367302002000010000602001000010000120037120051115020110099100401001000010000010010000011000000010000110032102108221196564000210109100001000040100120036120052120036120036120052
60204120051899000000100120036119503109459256010340102100011000030100100001000010795525736084611828501200271200511200511118960311237450100302002000010000602001000010000120051120096115020110099100401001000010000010010000011000010010000110032102108221196564000210109100001000040100120052120052120052120052120052
60204120051900000000000120036119495109459256010340102100011000030100100001000010795525736084611828501200111200521200511118810311241750100302002000010064602001000010000120051120051115020110099100401001000010000010010000011000000010000110032102135231196464000010109100001000040100120052120052120036120052120052
6020412005189910041176100120057119495109459256010340102100011000030100100001000010795705736084611828501200301200521200531118970191124185058630522203181000060200100001000012003512005111502011009910040100100001000001001000001100000001000011003210210822119647400080109100001000040100120052120052120036120052120052
60204120051899000000000120036119495109459256010340102100001000030100100001000010791355736084611775201201121202611204401120030311250650344303602021210214608461010610214120155120244115020110099100401001000010000010010000011000000310000010032102108221196564000210109100001000040100120052120052120052120036120052
60204120051899000018000012003711950310945925601004010210001100003010010000100001079552573608461182850120027120056120051112001031124215010030200200001000060200100001000012005112003511502011009910040100100001000001001000000100000001000011003210210822119656400020109100001000040100120052120052120036120052120036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

retire uop (01)cycle (02)03mmu table walk instruction (07)0f181e223f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)acafb5l1d cache miss ld nonspec (bf)c2cfd0l1i cache miss demand (d3)d5map dispatch bubble (d6)daddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
600251200578990000112003611948910944325600134001210001100003001010000100001079858573608461243440120027120051120035111903311244850010300202000010000600201000010000120051120035115002110910400101000010000010100001100000010000110314000159905171196694000210109100001000040010120052120052120052120036120052
600241200519000001112003611948410945925600104001210001100003001010000100001079769573608461257461120028120051120051111919311244850010300202000010000600201000010000120051120051115002110910400101000010000010100001100001010000010314000179401761196504000210109100001000040010120052120052120052120052120052
6002412005189900001120036119484109443256001340012100001000030010100001000010798585736084612574611200371200511200511119193112448500103002020000100006002010116100001200591200511150021109104001010000100000101000011000010100001003140007940617119669400000109100001000040010120036120036120038120052120052
60024120035900000011200361194841094592560013400121000110000300101000010000107985857360846124344112002812005112005111191931124485001030020200001000060020100001000012003612005111500211091040010100001000001010000110000031000011031400017990147119669400000109100001000040010120052120052120052120036120036
6002412003589900011120036119486109459256001340012100011000030010100001000010798585735293612574611200271200511200511119193112492500103002020000100006002010000100001200511200511150021109104001010000100000101000001000003100001103140001799116161196504000210100100001000040010120052120036120052120052120052
600241200518990001112003611948910945925600134001210001100003001010000100001079858573529361257461120011120051120035111919311244850010300202000010000600201000010000120051120051115002110910400101000010000010100001100001010000110314000179407171196694000210109100001000040010120036120036120036120052120052
6002412005189900011120036119484109459256001340010100011000030010100001000010798585736084612574611200271200961200511119033112778514673002020000100006002010000100001200511200351150021109104001010000100000101000011000000100000103140001799017141196694000210100100001000040010120052120052120052120052120036
600241200518990000112002011948410944325600104001210001100003001010000100001079858573529361257461120037120051120051111919311243750010300202000010000600201000010000120051120051115002110910400101000010000010100001100000010000010314000179906171196694000210109100001000040010120037120052120052120052120052
60024120035899000111200361194841094592560013400121000110000300101000010000107985857360846125746112002712005112003511191931124485001030020200001000060020100001000012005112003511500211091040010100001000001010000110000001000011031401401799061711966940002101018100001000040010120052120052120036120052120052
60024120051900000111200361194841094592560013400121000110000300101000010000107985857360846125746112003112005112005111191931124485001030020200001000060020100001000012003512003511500211091040010100001000001010000110000001000001031400079918171196694000210100100001000040010120052120036120052120052120052

Test 4: throughput

Count: 8

Code:

  ld1 { v0.1d, v1.1d }, [x6]
  ld1 { v0.1d, v1.1d }, [x6]
  ld1 { v0.1d, v1.1d }, [x6]
  ld1 { v0.1d, v1.1d }, [x6]
  ld1 { v0.1d, v1.1d }, [x6]
  ld1 { v0.1d, v1.1d }, [x6]
  ld1 { v0.1d, v1.1d }, [x6]
  ld1 { v0.1d, v1.1d }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3340

retire uop (01)cycle (02)03090e0f1e2223243a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)acafb5b6bbl1d cache miss ld nonspec (bf)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0e7eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602052673420110144100126716212102580100100800001008000050011688801267022672726727665036685801002001600002008000026727267071180201100991001008000080000010080000080000138800396104405110116112673311410780000800001002673226732267282673226708
160204267072000004400012669201119258010010080000100800005001174628026706267272673166543668980100200160000200800002673126727118020110099100100800008000001008000043800380398003861394405110116122671401414780000800001002672826708267322673226732
16020426707200000440000266922011925801001008000010080000500116888012670226727267076630366898010020016000020080000267312670711802011009910010080000800000100800004380038038800380004405110116122671001410780000800001002670826732267322670826728
1602042673120000044000126716010162580100100800001008000050011748871267062672726731665436665801002001600002008000026731267071180201100991001008000080000010080000438003900800006138430511011612267490014480000800001002673226708267322673226732
16020426731200000000002669200128462804921008000010080000500116908502668226707267316630366898010020016000020080000267312672711802011009910010080000800000100800000800380388003860000511011611267360140780000800001002670826732267282672826732
16020426727200010440001267160101925801001008000010080000500116908512670626731267076630366658010020016000020080000267272670711802011009910010080000800000100800004480039008003961384305110116222679801010780000800001002673226708267082670826732
16020426727200000440001267160011925801001008000010080000500117488712670626731267316654366898010020016000020080000267072670711802011009910010080000800000100800004380038038800000138430511011611268110014780000800001002673226732267082670826708
160204267072000000000126712011219258010010080000100800005001169085026706267272673166303668980100200160000200800002670726707118020110099100100800008000001008000043800380080038613844051101161126707000780000800001002670826728267082672826728
1602042670720000044000126716012019258010010080000100800005001169085026702267272673166303668980100200160000200800002673126707118020110099100100800008000001008000044800000388003800404305110116222670701010080000800001002672826784267322673226709
1602042672720001001001266922120102580100100800001008000050011747730267062670726737665436665801002001600002008000026727267271180201100991001008000080000010080000438000004180039003900511011611268390140780000800001002670826732267322673226732

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

retire uop (01)cycle (02)03090e0f1e22233a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)acafb5b6bbl1d cache miss ld nonspec (bf)cfd5map dispatch bubble (d6)ddfetch restart (de)e0eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600252672920010018100267122012162580010108000010800005011746280267022673026727668236689800102016000020800002672726727118002110910108000080000010800004380038039800396139435020616552672801048000080000102670826708267082672826732
160024267312000003090012671621212725800101080000108000050116888002670626707267276681366918001020160000208000026731267271180021109101080000800000108000043800380388003861394450204164326704141408000080000102673226708267282672826708
16002426707200000431101267122121162580010108000010800005011746280267062672726727668136745800102016000020800002672726727118002110910108000080000010800000800380388003861394350205165526728141478000080000102673226732267322673226732
16002426731200000308101267120121192580010108000010800005011690851267062672726727668136711800102016000020800002673126707118002110910108000080000010800004380054041800000138050204163326728141478000080000102673226732267322673226708
1600242673120000037510126716201162580010108000010800005011746280267062673126731668236696800102016000020800002673126707118002110910108000080000010800004380039038800396154445020416442672414048000080000102672826732267082673226728
1600242672720000001002703721119258001010800001080000501174887026682267312673166813671180010201600002080000267312672711800211091010800008000001080000438003800800386138050203163326724141448000080000102673226708267322672826732
160024267312000104741012671621102580010108000010800005011688801266832672726707668236711800102016000020800002673126727118002110910108000080000010800000800390388003860384450204162326728101478000080000102670826708267082670826732
16002426731200000441012671621102580010108000010800005011753211267062673126727697936708800102016000020800002671326707118002110910108000080000010800000800000398003961384350204164326728141478000080000102673226732267322672826708
16002426707200000408100267122012162580010108000010800005011746281267062673126731668236711800102016000020800002673126727118002110910108000080000010800004380039039800386138050203164426728141408000080000102673226732267322673226728
160024267312000003951002671201116258001010800001080000501173183026706267272670766813670880010201600002080000267312670711800211091010800008000001080000080038038800006139445020516552670401078000080000102670826728267322673226708