Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, 2 regs, 2D)

Test 1: uops

Code:

  ld1 { v0.2d, v1.2d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f1e22243a3f43464951schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst simd load (98)inst ldst (9b)9dl1d tlb access (a0)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)acafb5bbl1d cache miss ld nonspec (bf)c2cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)dfe0eaebec? ldst retires (ed)f5f6f7f8fd
6200529293220322011410469728760000242622000200020001000040016061285232926331020002000200029072292561161001100010000200002002022002424012893924568913309153206863076381812515112873316558138551579220002918829279292732931529169
6200429301219011000800456528748020242622000200020001000060016060285802924631020002000200229095290821161001100010000200042000002002026012826983469793108140207883086381619454312840716302136431569820002936029254293882931629355
620042926822001000000049262898500024269200020002000100007001606328891292993102000200020002908029123116100110001000020000200000200042401361597726868329814520692313338208464522836516422136061507320002921729330288222925529248
62004291942190110111500461328833020242292000200020001000070016065286282924631020002000200029137290041161001100010000200042002002000406012902922668653099150206223182381817474302836616292137611559520002928229390293752939929260
6200429212220011000000460728826020241702000200020021059770816060287122924431020002000200029134290961161001100010000200042002102006426212888910068803100147204973307381817524612835016291137171566320002921229273296262920829217
6200429317220010100600455928826000243162000200020001000150016094289952930882920022002200229141291271161001100010000200002000032000026012975918168943318049206933042381315494312833516437136561546820002920429325293232920429260
62004292912192110001210455128974022242152000200020001000030016056286052922831020002000200029192291311161001100010000200002002002002420012910927968553069047206473039381921504312842716623136331580320002932629224293592941129297
6200429163219010000600456628828000242592000200020001000040016059286132937431020002000200029239291621161001100010001200042002002000424012933919268793081149205583087382112475412881216356138171574020002920929295292032920929256
620042927022002000001046322893902024143200020002000100005001606228682293588102000200020002911629183116100110001000020004200203200042401290891066870309214620678305938199444312828916499139841576420002931229323292242936029318
62004292302190110000004565285180002411220002000200010000110816081286422929931020002000200029089290511161001100010000200062000022002406013120916968773098148206573112381717404612843116494136891563020002927329311292832935929220

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.2d, v1.2d }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0057

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f18191e1f22243a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
60205120053899111010040102120042967061097462570103401041000220000301001000020000104272655733724346568401200170120057120041112129311251560100302002000010000602002000010000120057120041115020110099100401001000010000010020003302000300220000220210321011611119830400040602000040100120058120058120054120054120042
6020412005789910000008010012003896718109742257010640104100012000030100100002000010426917573372434658000120029012004112005711214731125116010030200200001000060200200001000012005312004111502011009910040100100001000001002000230200031022000022022032101161111982640004101092000040100120042120058120058120058120054
60204120053899101000020101120038967221097422570106401021000220000301001000020000104258735733724346533601200290120057120057112129311251160100302002000010000602002000010000120057120053115020110099100401001000010000010020003222000300220000020200321011611119830400026652000040100120054120054120058120042120058
602041200578991110000401021200389672210973025701064010410001200003010010000200001042587357335323465684012003301200411200531121453112499601003020020000100006020020000100001200411200531150201100991004010010000100000100200022220002002200002222003210116111198144000401092000040100120058120058120054120058120058
60204120041899101000040002120042967221097462570103401041000220000301001000020000104269175732956346568401200330120053120057112129311251160100302002000010033602002000010000120041120057115020110099100401001000010000110020002322000251520000022210321011611119830400046092000040100120058120058120058120042120554
602041200578991010000401021200429670610974225701064010410001200003010010000200001042691757337243465336012001701200571200411121293112499601003020020000100006020020000100001200531200411150201100991004010010000100000100200023220004122200002202003210116111198264000210052000040100120042120042120058120058120042
6020412005790010100004000212003896722109745257011940102100022000030100100002000010427265573372434658000120017012004112005711214531125246010030200200001000060200200001000012005712004111502011009910040100100001000001002000322200020122000022221032101161111983040004101052000040100120054120058120054120054120054
602041200538991100000200001200269670610973025701064010210002200003010010000200001042726557337243465336012001701200411200571121293112515601003020020000100006020020000100001200571200531150201100991004010010000100000100200022020002002200002222203210116111198304000210652000040100120042120058120054120054120058
6020412004189911000002010212004496722109730687025440128100022000030100100002000010427265573372434653360120033012008112005311214531125156010030200200001000060200200001000012004112005311502011009910040100100001000001002000232200020122000222221032101161111983040002101052000040100120054120058120042120042120058
60204120041899101100040001120038967061097462570106401041000220000301001000020000104272655733724346580001200780120041120057112129311251560100303022000010000602002000010000120041120055115020110099100401001000010000010020004322000300220000222200321011611119830400040092000040100120042120054120058120058120058

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0053

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f1e22233a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2cdcfd0l1i cache miss demand (d3)d5map dispatch bubble (d6)dbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
6002512005389900000400212004496647109746257001640014100022000030010100002000010425896573372434654080120033120057120053112164311253760010300202000010000600202000010000120057120053115002110910400101000010000010200033220003002200002222003140006160451198324000410692000040010120058120042120042120042120042
6002412034889910000210112003896641109736257001340012100002000030010100002000010424226573324434648800120011120051120047112162311253160010300202000010000600202000010000120051120035115002110910400101000010000010200022020002002200002222103140004160451198324000210652000040010120054120058120042120058120042
6002412004189910100410212003896647109742257001640012100022000030010100002000010425896573372434654361120017120041120053112168311253760010300202000010000600202000010000120097120041115002110910400101000010000010200000220004103200000020003140004160451198224000401052000040010120058120058120058120058120058
600241200578991100041021200269664710974225700164001410001200003001010000200001042589657337243465060112003312004112005311215231125336001030020200681000060020200001000012005712005311500211091040010100001000001020003222000301220000220200314000425058120059400020602000040010120058120057120054120601120054
60024120041899102004002120565966431097422570016400141000120000300101000020000104245045756782346780301200291200531200531121683112521600103002020000100006002020000100001200531200531150021109104001010000100000102000432200040222000002021031400041604511983240004101092000040010120048120048120048120048120052
600241200358990000040001200369664110974025700134001210000200003001010000200001042537457334363464880012001112005112005111216231125316001030020200001000060020200001000012005112004711500211091040010100001000001020000022000000020000000000314014051604411982640004101092000040010120054120058120042120058120058
600241200578991100080021200289663110973025700164001410002200003001010000200001042554857329563465408112002912005312005711215231125336001030020200001000060020200001000012005312005311500211091040010100001000001020002222000301220000222210314000416044119816400040652000040010120054120054120058120058120042
6002412005789910000200212004296642109740257001340010100012000030010100002000010423974573324434652341120027120051120047112162311251560010300202000010000600202000010000120051120047115002110910400101000010000010200032220003002200002202203140003160441198324000410692000040010120042120058120058120058120058
600241200539001020040021200429664710974625700164001210002200003001010000200001042554857337243465408112003312005712005711215331125336001030020200001000060020200001000012005712005311500211091040010100001000001020002222000301220000222200314000516044119816400020092000040010120058120058120058120058120151
6002412004190011101400112002093975109724257001340010100012000030010100002000010425026573266634648801120027120037120051112162311253160010300202000010000600202000010000120047120047115002110910400101000010000010200024220000000200002000003140005160461198264000210002000040010120036120036120048120052120048

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.2d, v1.2d }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f2223243a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5l1d cache miss ld nonspec (bf)c2branch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
602051200528990100100201000120036967161097402570103401021000120000301001000020000104282205733436346562601200271200511200511121393112509601003020020000100006020020000100001201051200831150201100991004010010000100000100200000220000000200002200032102161111982440002101002000040100120052120053120052120052120052
602041200518990000100200000120037967161097402570103401021000120000301001000020000104267435733436346562601200271200511200511121393112509601003020020000100006020020000100001200511200511150201100991004010010000100000100200000220000000200002200032101161111982440002101092000040100120052120052120052120052120052
6020412005189900011002010001200369326910974025701034010210001200003010010000200001042674357326663465156112001112005112005111213931125096010030200200001000060200200001000012006112005311502011009910040100100001000001002000002200020030200002200032101161111982440002101092000040100120052120052120052120052120052
602041200518990000000200000120036967161097402570103401021000120000301001000020000104267435733436346562601200271200511200511121393112509601003020020000100006020020000100001201001200961150201100991004010010000100000100200040220000000200002200032101161111982440002101092000040100120052120052120052120052120052
602041200518990000000201000120036967171097402570103401021000120000301001000020000104267435733436346562601200271200511200511121393112509601003020020000100006020020000100001200551200861150201100991004010010000100000100200000220000000200002200032101161111982440002101092000040100120052120052120036120052120052
602041200519000000000201000120036967161097402570103401001000120000301001000020000104267435733436346562601200271200511200511121393112509601003020020000100006020020000100001201281200671150201100991004010010000100000100200000220000000200002200032381161111982440002101092000040100120052120052120052120052120052
6020412005189900000002010001200369671610974025701034010210001200003010010000200001042674357326663465156012002712005112003511213931125096010030200200001000060200200001000012010912006611502011009910040100100001000001002000002200000027200002200032101161111982440002101092000040100120052120052120052120052120052
602041200518990000000200000120036967161097402570103401021000120000301001000020000104267435733436346562601200271200511200511121403112509601003020020000100006020020000100001200721200521150201100991004010010000100000100200000220000000200002200032101161111982440002101092000040100120052120052120052120052120052
602041200518990000100201001120036967161097402570103401021000120000301001000020000104267435733436346562601200271200511200511121393112509601003020020000100006020020000100001200881200681150201100991004010010000100000100200000220000000200002000032101161111982440002101092000040100120052120052120036120052120052
6020412005189900000002010001200369671610974025701034010210001200003010010000200001042674357326663465626012001112005112005111213931125096010030200200001000060200200001000012009912005321502011009910040100100001000011002000002200000002000020010321011611119824400021010132000040100120052120052120052120052120052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)0f181e22233a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)acafb5l1d cache miss ld nonspec (bf)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
60025120035902114210112004096641109724257001040012100002000030010100002000010425374573343634648801120027012005112005111216231125156001030020200001000060020200001000012003512004711500221091040010100001000011020000020000002000020000314031634119810400020092000040010120052120052120052120036120052
6002412003589900001011200369664110974025700134001210001200003001010000200001042397457326663465234112002701204051200511121623112531600103002020000100006002020000100001200471200471150021109104001010000100000102000002000000200002200031404163311982240002101092000040010120052120036120036120048120052
600241200478990002101120020966411097242570013400121000120000300101000020000104257225733436346488011200270120035120051112162311253160010303972000010000600202000010033120038120047115002110910400101000010000010200002200001020000220003140416351198324000010692000040010120052120052120048120052120048
6002412003589900020011200209397510973625700134001210000200003001010000200001042397457332443465234112013001200511200511121583112515600103002020066100006002020000100001200351200351150021109104001010000100000102000022000000200002000031403165511981040002101092000040010120048120051120036120036120037
600241200519000002001120036966411097422570013400101000120000300101000020000104250265732666346523411200110120047120047112162311251560010300202000010000600202000010000120035120047115002110910400101000010000010200002200002320000020003140516531198104000010002000040010120048120048120036120048120052
600241200479000002001120036939751097402570013400121000020000300101000020000104253745732666346523411200270120051120051112162311252560010300202000010000600202000010000120052120047115002110910400101000010000010200002200000020000220103140416331198104000210002000040010120052120052120052120036120036
60024120047899000200012003296641109740257001340012100012000030010100002000010423974573343634648801120027012005112003511216231125316001030020200001000060020200001000012005112004711500211091040010100001000001020000220004222532001002000314041644119826400026652000040010120048120052120036120052120052
60024120035899000140011200369664110974125700134001210002200003001010000200001042397457334363465350112003401200961202211122439112647605323002020000100006002020126100961202601204261150021109104001010000100000102000022000010200000200031405164411981040002101052000040010120052120054120052120048120053
60024120035899000140011200369664110974025700134001210001200003001010000200001042537457332443464880112006601200521200521121719112535600103002020000100006002020000100001200351200351150021109104001010000100000102000002000000200002200031402165411982640002101092000040010120036120052120052120036120052
600241200358990002100120032966411097362570010400121000120000300101000020000104253745732666346523411200110120035120035112158311251560010300202000010000600202000010000120047120035115002110910400101000010000010200004200000020000020003140416531198264000010092000040010120052120036120052120052120036

Test 4: throughput

Count: 8

Code:

  ld1 { v0.2d, v1.2d }, [x6]
  ld1 { v0.2d, v1.2d }, [x6]
  ld1 { v0.2d, v1.2d }, [x6]
  ld1 { v0.2d, v1.2d }, [x6]
  ld1 { v0.2d, v1.2d }, [x6]
  ld1 { v0.2d, v1.2d }, [x6]
  ld1 { v0.2d, v1.2d }, [x6]
  ld1 { v0.2d, v1.2d }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f181e22233a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
1602055340240000000044000533590112162516010010016000010016000050023345351533785339453374333213333321601002001600002001600005337453374118020210099100100800008000011001600200431600381006016003800043005110116115344814071600001005339553375533955339953399
160204533944000000104410153383211025160100100160000100160000500233626415337753381533823332533335616010020016000020016000053374533941180201100991001008000080000010016000000160039020016000060390005110116115339614071600001005339953395533955339953399
16020453398399000000440005335920019251601001001600001001600005002334106153373533985339833296333356160100200160000200160000533945339411802011009910010080000800000100160000043160000000016003800043005110116115347414041600001005339553375533995337553375
1602045339839900000044002533832111925160100100160000100160000500233626405337353374533743329633335616010020016000020016000053394533941180201100991001008000080000010016000004316003800039160038013843005110116115346301471600001005339953375533995337553375
160204533984000000004410153359201025160100100160000100160000500233289715346053403533833329633333216010020016000020016000053374533941180201100991001008000080000010016000004316000000039160000013943005110116115352001001600001005339953399533755339953399
1602045339839900000044000533830120025160100100160000100160000500235227515337353398533983329633335616010020016000020016000053374533941180201100991001008000080000010016000000160038020016003861590005110116115352271471600001005339953395533955339953399
16020453394400000000440005338300116251601001001600001001600005002352275153373533985339833296333332160100200160000200160000533985339411802011009910010080000800000100160000001600390000160039613844005110116115367114041600001005337553399533755339553375
160204533944000010002420015335921019251601001001600001001600005002336264053373533985337433296333356160100200160000200160000533985339411802011009910010080000800000100160000001600390004116003900380005110116115354801401600001005337553399533995337553375
1602045339840000000044001533660111925160100100160130100160000500233626415337353374533943331733335616010020016000020016000053398534001180201100991001008000080000010016000004416003800038160038613800051101161153501141401600001005339553399533755337553399
16020453398400000000000053359201025160100100160000100160000500233396205337353394533743332133335616010020016000020016000053398533941180201100991001008000080000110016000004316003800039160000013944005110116115348701471600001005337553375533995337553375

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6674

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)0e0f191e1f22243a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)a5ld unit uop (a6)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)c2branch mispred nonspec (cb)cfd2d5map dispatch bubble (d6)ddfetch restart (de)e0eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
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16002453394400000104501005338921812122516001010160000101600005023412511533695337453394333343333691600102016000020160000535235340211800211091010800008000001016000003901600390042160039603943005020119169753390602160000105337553395533905339053395
160024533744000000045000253379012120251600101016000010160000502367024053369533945339433339333354160010201600002016000053383533891180021109101080000800000101600000390160039000160035013900050201095279533911004160000105339553395535245337553390
160024533944000000000002533740120122516001010160000101600005023320841533495337453394333193333541600102016000020160000533995338911800211091010800008000001016000000016000000391600390139430050201171669533911004160000105337553395533955339553395
1600245339440000000480002533792121216251600101016000010160000502334125053364533995339433334333374160010201600002016000053406533891180021109101080000800000101600000001600000001600006040430050201071679533911004160000105339553395533955339553375
16002453394400000004500025335921212162516001010160000101600005023325490533495339453377333373333741600102016000020160000534075338911800211091010800008000001016000004301600000039160000613900050201191679533911064160000105339553395533955339553395
16002453394399000004100025337921212162516001010160000101600005023325491533695339453394333393333751600102016000020160000534035338911800211091010800008000011016000003901600390039160000600001502010716795339110104160000105338053375533955339553395
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1600245339440000000450002533792121816251600101016000010160000502333859153369533745337433339333374160010201600002016000053522533871180021109101080000800001101600000390160039003916000001390005020119169953386044160000105339053375533955339553375
160024533744000001045000253359012016251600101016000010160000502367024053369533945339433339333374160010201600002016000053395533741180021109101080000800000101600000390160035003916003961390005020109167953371064160000105337553390533755337553390