Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, 2 regs, 2S)

Test 1: uops

Code:

  ld1 { v0.2s, v1.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03mmu table walk instruction (07)09l2 tlb miss instruction (0a)0e0f1e2223243a3f464951schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst simd load (98)inst ldst (9b)9dl1d tlb access (a0)l1d cache miss ld (a3)ld unit uop (a6)acafb5bbl1d cache miss ld nonspec (bf)c2cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaebec? ldst retires (ed)? simd retires (ee)f5f6f7f8fd
6200529297220171171126910045922880910242641000100010005000700160532882529383310100020001000290812926411610011000100001000210000100021201361296816864328194720668331838147424028405161661391315708100010002929029244292912922229280
62004293152201301511413100460928946002438010001000100050002001606328494292173101000200010002915929026116100110001000010002100001000213012952985870593215114120648310338249373728771162621356714993100010002920129276292112929529274
62004293332212001610365100464328775002431010001000100050008001605328571291713101000200010002919929030116100110001000010002100001000213012932907770843304941206503289381711403628328157271381515103100010002935229182291782918329238
62004292612191902100107100489328762002431210001000100050002001607628796294063101000200010002909029018116100110001000010002100001002212013026989668753183638207993135381410413528383157241370215530100010002923129345293852933429312
620042938122017015002000497228945012425210001000100050003001608428532293363101000200010002904229085116100110001000010002100001000202013032985368753362936205573142382110373428333161851338115682100010002924029283291632911229165
620042917921914015006100500828778002426410001000100050007001605428539292473101000200010002899829059116100110001000010002100001001212012809914571543098123620596325038218383828438157231367814963100010002923929340292302919529267
620042918821815018102610046532882400242321000100010005000700160822882129162310100020001000291072912211610011000100001000210010100020301298292486896313893820557313738157353728390160591368715605100010002913429391292552923229346
6200429416220140140015100461329000002426010001000100050004001605228608292323101000200010002902729057116100110001000110003100001001203012861939868713073841205543270382010354228333155771350614838100010002921429201291562924029348
62004292262191501300287100486828799002433810001000100050001001604128567291943101000200010002919229063116100110001000010003100001000202013666920769043042940205683108382517423728343157481331615138100010002932029204292182922829268
62004292492201601611267100466228761002435210001000100050008001606528588292303101000200010002904429016116100110001000010003100101000203012938915569443100836206553045381210433928316162821344815503100010002919729304293072920828933

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.2s, v1.2s }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0061

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f18191e1f22233a3f43494d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
60205120049900111000063800011200380111951610946825601064010410003100003010010000100001079459573656661182971120037012006112006111190731124145010030200200001000060200100001000012005312006111502011009910040100100001000001001000122100030011000012110000321011211111967340006665100001000040100120062120062120062120062120062
602041200618991010000301001200461111951610946825601094010610002100003010010000100001079459573656661182970120037012013412029311190731124175010030200200001000060200100001000012006112006111502011009910040100100001000001001000212100010121000011110000321011101111967340006065100001000040100120159120054120064120062120062
602041200539001110000300001200461111951610946825601064010610003100003010010000100001079459573618261182970120029012005312006111189931124155010030200200001000060200100001000012006112006111502011009910040100100001000001001000222100030021000112110000321011101111967340004665100001000040100120054120164120062120062120062
602051200498991100000300011200461011949710946125601094010410002100003010010000100001079464573642261193800120073012005312006111190731124145010030200200001000060200100001000012006112006111502011009910040100100001000001001000111100030021000012110000321011211111967340006605100001000040100120065120057120062120062120065
602041200618991010000300001200461111951610946825601094010610002100003010010000100001079459573656661193800120029012006112006111190731125205010030200200001000060200100001000012006112006111502011009910040100100001000001001000221100030121000111110000321011211111967340006665100001000040100120062120062120062120062120094
602041200538991110000201001200381011951610946825601094010610003100003010010000100001079479573618261193800120026012004912005311189931124695010030200200001000060200100001000012006112006111502011009910040100100001000001001000221100040121000012111000321011101111967340004665100001000040100120062120062120054120062120050
602041200539001110000201011200380111953410946925601064010610003100003010010000100001079464573618261193800120029012005512005311189931124375010030200200001000060200100001000012006112004911502011009910040100100001000001001000212100030121000112110000321011101111966240004665100001000040100120062120062120054120062120062
602041200539001110000200111200381011949710946325601094011110002100003010010000100001079459573656661193800120025012006112006111189931124265010030200200001000060200100001000012006112005311502011009910040100100001000001001000122100030111000112112000321011101111967340006665100001000040100120054120062120054120062120062
602041200538991000000700111200461111951610951725601094010410003100003010010000100001079459573656661193800120037012005312005311190231124315010030200200001000060200100001000012006112005311502011009910040100100001000011001000121100020121000111112000321011211111967340006665100001000040100120062120054120062120054120062
602041200538991100000300101200461111949310946125601094010610003100003010010000100001079464573618261182970120029012005312006111190731124825010030200200001000060200100001000012006112006111502011009910040100100001000001001000121100020021000112111000321011211111966240006665100001000040100120062120062120062120062120054

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

retire uop (01)cycle (02)03mmu table walk data (08)090e0f1e22233f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acafb5l1d cache miss ld nonspec (bf)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
600251200518990100110120036119484109459256001040010100001000030010100001000010797695735293612574612002712005112005111191931125025001030020200001000060020100001000012005112005111500211091040010100001000001010000001000000010000103140699221196694000210109100001000040010120055120052120036120052120052
600241200518990010101012003611948910944325600134001210001100003001010000100001079858573608461243441200111200511200511119193112497500103002020000100006039410000100001200361200511150021109104001010000100001101000001100000001000011314029962119669400020100100001000040010120052120052120052120052120036
600241200518990000110120244119484109459256001340012100011000030010100531014710894225736084612574612001112005112005111191931124875231930020200001000060020100001000012005112005111500211091040010100001000001010000211000000010000113140299261196694000210100100001000040010120036120052120052120052120036
60024120051899000040012003611948410945925600104001210001100003001010000100001079769573529361243441200271200511200511119193112474500103002020000100006002010000100001200511200511150021109104001010000100000101000001100000001000011314039936119669400020109100001000040010120052120052120052120052120052
600241200518990000010120020119484109443256001340012100011000030010100001000010798585736084612574612008012005112003511191931124825001030020200001000060020100001000012005112005111500211091040010100001000001010000011000000010000113140694621196694000210109100001000040010120052120052120052120052120052
600241200518990000110120036119489109459256001340012100011000030010100001000010797695736084612434412002712003512005111191931125195001030020200001000060020100001000012009612005111500211091040010100001000001010000011000000010000113140699221196694000210109100001000040010120052120052120052120052120052
60024120051899000001012003611948410945925600134001210001100003001010000100001079858573608461257461200111200511200511119193112457500103002020128100006002010000100001200511200511150021109104001010000100000101000001100000001000011314029922119669400021009100001000040010120036120052120036120052120052
600241200518990000100120036119484109459256001040012100011000030010100001000010798585736084612574612002712005112005111191931125005001030020200001000060020100001000012005112005111500211091040010100001000001010000011000000010000113140699621196504000210109100001000040010120052120036120052120036120052
6002412005189900007101200361194841094602560013400121000110000300101000010000107976957360846125746120027120052120051111919311249050010300202000010000600201000010000120051120051115002110910400101000010000010100000010000110100001131402942311966940002009100001000040010120052120061120055120052120052
6002412005193010001310120151119484109443256001340012100011000030298100001004910798675736228612590212002712005112005211190331125195001030020200001000060020100001000012003512005111500211091040010100001000011010000001000000010000103140699221196694000210109100001000040010120052120052120052120052120052

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.2s, v1.2s }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0054

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f2223243a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)int prf full (71)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
602051200518990000000010100012002011951110944325601034010210001100003010010000100001079126573623061183361120011012005112005111190703112407501003020020000100006020010000100001200511200511150201100991004010010000100000100100000110000105010000101000003210011081111970740000131012100001000040100120052120055120036120108120055
6020412005489900000000001000120020119503109443256010340102100011000030100100001000010793965735293611828511200300120054120097111898031123745010030200200001000060200100001000012005412003511502011009910040100100001000001001000001100000000100001010000032100110811119666400020012100001000040100120052120052120055120055120055
60204120035899000000001000001200391195091094612560106401021000010000301001000010000107939657362306118285112003501200541200351119060311240750100302002000010000605781000010000120054120051115020110099100401001000010000010010000011000000001000000000000321001121111196464000013100100001000040100120052120052120036120037120055
60204120054899000000001000001200361194951094612560100401021000110000301001000010000107912657352936118285112001101200541200511119080311241750100302002000010000602001000010000120054120035115020110099100401001000010000010010000011000000031000010100000321001135111196664000213012100001000040100120036120055120036120055120055
60204120054899000000001000001200201195091094432560100401021000110000301001000010000107912657362306118285112003001200541200511119120311237450100302002000010000602001000010000120054120035115020110099100401001000010000010010000001000001001000010100000321001135111196664000213012100001000040100120036120052120052120036120055
60204120054899000000001000001200391194951094612560103401001000110000301001000010000107912657362306118285112002701200351200511119130311237450100302002000010000602001000010000120051120051115020210099100401001000010000010010000001000000001000010100000321001121111196664000213100100001000040100120055120055120036120055120036
60204120054899000000003000001200391194951094592560103401021000110000301001000010000107955257362306117599112003001200541201021119820311240750100302002000010000602001000010000120054120035115020110099100401001000010000010010000011000000001000010100000321001135111196664000210100100001000040100120052120052120052120036120055
602041200358990000000010010001200391195091094432560100401021000110000301001000010000107939657352936117599112003301200541201201118990311240750100302002000010000602001000010000120054120100115020110099100401001000010000010010000011000000001000010000000321001108111196464000010012100001000040100120036120055120052120055120055
6020412005489900000000100000120039119509109461256010040102100011000030100100001000010791265736230611828511200270120054120051111902031124075010030200200001011860200100001000012005512003711502011009910040100100001000001001000200100000000100000010000032100112111119666400021009100001000040100120036120055120055120055120055
60204120054900000000001000001200391195091094432560100401001000110000301001000010000107912657362306118285112002701200541201221119010311237450100302002000010000602001000010000120051120051115020110099100401001000010000010010000001000000001000010100000321001171111965640002131012100001000040100120036120055120055120056120055

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0053

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f1e1f22233a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)91inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
6002512005389911111200011200261194861094612560013400141000210000300101000010000107987857361826125852012001712005312005611192431124505001030020200001000060020100001000012004112005311500211090104001010000100000101000121100010211000011010314011994211967440004068100001000040010120042120060120066120057120057
600241200538991000010100120041119489109463256001640012100021000030010100001000010798705736326612585211200321200561200411119093112438500103002020000100006002010000100001200531200411150021109010400101000010000010100022110003004100001111131402992411967140004608100001000040010120042120057120057120057120042
600241200568991110020000120038119486109449256001640014100021000030010100001000010798785736326612585211200171200531200531119213112438500103002020000100006033810107100001200531200531150022109110400101000010000010100031010001011100001101131405996411965940002665100001000040010120054120042120054120057120054
600241200538991110020001120038119489109463256001640014100011000030010100001000010798785735593612350011200171200531200531119213112438500103002020000100006002010000100001200531200411150021109010400101000010000010100023110001004100001111231403994211965940004968100001000040010120057120057120057120042120042
600241200568991100110001120041119484109449256001640014100021000030010100001000010799065736326612585211200321200411200531119093112453500103002020000100006002010000100001201011200411150022109010400101000010000010100021110001411100001111031403992411967140002965100001000040010120057120054120042120042120042
600241200419001110010101120041119489109461256001640014100021000030010100001000010798785736182612585211200321200561200411119243112438500103002020000100096002010000100001200561200531150021109010400101000010000010100023110003001100001101031404994211967440004660100001000040010120057120057120054120057120057
6002412005689910110110000120026119484109463256001340014100011000030010100001000010799065735593612585211200321200411200561119243112438500103002020000100006002010000100001200531200531150021109010400101000010000010100022110002011100001111131402992411967140004065100001000040010120054120054120054120042120054
600241200538991110010000120026119489109449256001640012100011000030010100001000010799235735593612585211200321200561200561119093112453500103002020104100006002010000100631200411200531150021109010400101000010000010100013110001011100001101131402992411967440004908100001000040010120057120057120042120042120057
600241200588991100020000120041119486109463256001640014100021000030010100001000010798705736326612350001200321200561200561119813112438500103002020000100006002010000100001200561200531150021109010400101000010000010100011110002011100001111031402992411967440004060100001000040010120057120057120057120057120057
600241200418991010020100120026119489109461256001640014100021000030010100001000010799065736326612365301200321200561200561119243112453500103002020000100006002010000100001200411200591150021109010400101000010000010100012110002111100000111131404994211965940004008100001000040010120057120057120057120058120042

Test 4: throughput

Count: 8

Code:

  ld1 { v0.2s, v1.2s }, [x6]
  ld1 { v0.2s, v1.2s }, [x6]
  ld1 { v0.2s, v1.2s }, [x6]
  ld1 { v0.2s, v1.2s }, [x6]
  ld1 { v0.2s, v1.2s }, [x6]
  ld1 { v0.2s, v1.2s }, [x6]
  ld1 { v0.2s, v1.2s }, [x6]
  ld1 { v0.2s, v1.2s }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f1e22233a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602052674020010111520103267210771825801001008000010080000500116772202671126736267366637366948010020016000020080000267362673611802011009901001008000080000010080020194380058000618003960194319151104163326711130080000800001002671526737267372671526715
160204267362001111182102266992792025801001008000010080000500117017902671126736267366637367008010020016000020080000267392673611802011009901001008000080000010080020190800591006180040615843190511031624267331313580000800001002673726737267152673726737
16020426736201100003511022672107719258010010080000100800005001167999026711267362671466593669480100200160000200800002673626736118020110099010010080000800000100800192143800590012180039616043190511011623267331313580000800001002690126724267422673726737
16020426737200101004810226699377202580100100800001008000050011679990267112673626714665936704806342001600002008000026736267141180201100990100100800008000001008002019438005900260800426119019151103163126733013580000800001002673726737267372673726737
1602042673620011100397102267313071925801001008000010080000500116964802671126714267366637366818010020016000020080000267362671411802011009901001008000080000010080020204380019101638004061614319051102161226733130580000800001002673726737267392673726737
16020426714201110004171032672120720258010010080000100800005001170722026711267362673666593670880100200160000200800002671426736118020110099010010080000800000100800191943800591002180000005943190511031632267111313080000800001002671526737267372671526737
16020426736201100003720002672100720258010010080000100800005001167371026689267362673666593670480100200160000200800002673626714118020110099010010080000800000100800191943800601002180039615943190511041643267331313580000800001002671526715267152673726737
160204267362001100039100226699107192580100100800001008000050011677220267112671426714665936700801002001600002008000026736267141180201100990100100800008000001008001920080059100618004061580190511011624267331313080000800001002673726715267152671526738
16020426715200101003900122672130914025801001008000010080000500116737102668926714267366637371018010020016000020080000267432674111802011009901001008000080000010080020190800580026480040615943191511011613267111313580000800001002673726737267152671526737
1602042673620010000409012267210701925801001008000010080000500116923502671226714267366637368438010020016000020080000267362673611802011009901001008000080000110080020190800601016180040615943181511011633267331313580000800001002671526737267372673726737

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f1e22233a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2cdcfd5map dispatch bubble (d6)daddfetch restart (de)e0eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600252672420000101136810326717018017258001010800001080000501173183026702267272672266533679980010201600002080000267072672211800211091010800008000011080019204180057001598003861350000502022160176267040608000080000102672326743267302670826723
1600242672720700000098103267170018162580010108000010800005011706820267072673226732666036720800102016000020800002673226714118002110910108000080000010800191908005710059800380157421910502017160817267299928000080000102671526718267152673326733
16002426714201111100147000267172181816258001010800001080000501186689026707267322671466783672180010201600002080000267322673211800211091010800008000011080000039800390003980039003543000502017160178267299928000080000102671526733267332671526733
1600242673220011100033910326699218181625800101080000108000050117309302668926714267146677367188001020160000208000026732267321180021109101080000800000108002019428005700259800006157421910502017160176267119928000080000102673326733267332673326733
1600242673220010010195102267172181816258001010800001080000501171570026707267142673266803671780188201603782080000267322674111800211091010800008000001080020204280019001598003860574218105020141601717267246608000080000102670826728267232672826728
1600242670720000000041102267122121812258001010800001080000501173183026702267272670766533670780010201600002080000267072672711800211091010800008000001080000039800390704580000010430005020171601717267299008000080000102671526733267332673326715
160024267332011100004210326699200162580010108000010800005011706821266892673226732666036822800102016000020800002673226714118002110910108000080000010800202042800570116280038601942190050208160817267299908000080000102673326715267152673326733
1600242673220011110039510026720101802580010108000010800005011715701267072673226732667736862800102016000020800002673226732118002110910108000080000010800000398003500008003501043000502017160177267170908000080000102673326733267332673326733
1600242673220011000092103267172181816258001010800001080000501174390126689267322684166793671280010201600002080000267322673211800211091010800008000001080021190800570026380000615742190050208160616267119028000080000102673326733267332673326733
16002426732200100100890012671721818162580010108000010800005011715701266892673226803666836712800102016000020800002673226732118002110910108000080000010800212042800580106280000015842190050201716017172685610048000080000102672826728267282672826723