Firestorm: LD1 (multiple, 2 regs, 4H) measurements

Code:

  ld1 { v0.4h, v1.4h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	3a	3f	43	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
62005	28472	214	1	1	0	1	2	1	0	0	0	0	3	1	5180	28468	0	0	0	23339	1000	1000	1000	5000	6	1	0	16056	28089	28498	3	10	1000	2000	1000	28418	28129	1	1	61001	1000	1000	0	1004	2	2	1003	2	1	2	1000	2	2	2	1	2	13549	9651	7128	3204	0	62	19894	3168	3826	14	48	48	28086	14984	12809	14132	1000	1000	28628	28082	28615	28553	28243
62004	28544	213	1	1	0	1	1	1	0	0	0	0	3	0	4867	28097	0	0	0	23257	1000	1000	1000	5000	0	1	0	16084	28101	28622	3	10	1000	2000	1000	28481	28696	1	1	61001	1000	1000	0	1002	3	3	1003	32	0	1	1000	2	1	2	1	2	13478	10052	7108	3216	0	48	19915	3201	3829	23	57	49	28007	14782	12726	13906	1000	1000	28416	28575	28519	28457	28697
62004	28388	211	1	1	1	1	1	0	0	0	0	0	4	0	4870	27953	0	0	0	23593	1000	1000	1000	5000	5	0	0	16075	28093	28587	3	10	1000	2000	1000	28153	28432	1	1	61001	1000	1000	0	1002	3	2	1002	2	2	1	1001	2	2	2	1	2	13692	9462	7107	3243	1	48	19839	3240	3828	20	46	54	28080	15124	12963	14126	1000	1000	28598	28639	28532	28494	28722
62004	28222	211	2	1	1	0	1	1	0	0	0	0	3	0	4834	28220	0	0	0	23824	1000	1000	1000	5000	5	1	0	16058	28117	28533	3	10	1000	2000	1000	28435	28398	1	1	61001	1000	1000	0	1001	2	2	1003	4	1	2	1001	2	1	3	1	1	13351	9671	7199	3340	1	48	19894	3206	3819	17	55	52	28125	15122	12435	13559	1000	1000	28685	28527	28542	28475	28579
62004	28692	213	1	1	1	1	1	1	0	0	0	0	4	0	4954	28355	0	0	0	23481	1000	1000	1000	5000	3	0	0	16082	28144	28549	3	10	1000	2000	1000	28608	28522	1	1	61001	1000	1000	0	1002	2	3	1002	6	1	4	1000	2	1	2	1	0	13141	9798	7046	3348	0	55	19558	3208	3825	20	48	51	27878	15080	12666	14384	1000	1000	28391	28477	28437	28170	28185
62004	28525	212	0	1	1	1	1	1	1	1	0	0	4	1	4849	28267	0	0	0	23503	1000	1000	1000	5000	0	1	0	16088	28166	28577	3	10	1000	2000	1000	28423	28462	1	1	61001	1000	1000	0	1001	2	3	1003	1	1	2	1000	2	1	3	1	0	13259	9825	7019	3304	0	44	19905	3158	3822	13	52	51	28109	14932	12590	14205	1000	1000	28822	28220	28772	28237	28583
62004	28548	212	1	1	1	1	1	1	0	0	0	0	3	0	5017	28190	0	0	0	23402	1000	1000	1000	5000	2	1	0	16061	28229	28734	3	10	1000	2000	1000	28490	28552	1	1	61001	1000	1000	0	1001	3	3	1003	1	0	5	1000	2	1	2	1	2	13948	9858	7107	3419	0	42	19628	3152	3817	12	51	46	28085	15116	12264	14396	1000	1000	28534	28602	28500	28465	28373
62004	28712	212	0	1	1	1	1	1	0	0	0	0	3	0	4883	28267	0	0	0	23357	1000	1000	1000	5000	2	1	8	16081	28301	28517	3	10	1000	2000	1000	28533	28527	1	1	61001	1000	1000	0	1002	2	2	1001	2	1	2	1002	2	2	2	1	1	13664	9750	7080	3377	1	47	19604	3201	3829	16	50	51	28071	14083	12818	14369	1000	1000	28506	28584	28704	28577	28745
62004	28427	213	1	1	1	1	1	1	0	0	0	0	4	0	5156	28291	0	0	0	23491	1000	1000	1000	5000	0	0	0	16077	28218	28526	3	10	1000	2000	1000	28145	28492	1	1	61001	1000	1000	0	1003	2	2	1003	32	1	8	1000	2	1	3	1	2	13085	9480	7072	3366	0	50	19657	3222	3823	18	43	54	28114	15150	12536	14185	1000	1000	28213	28536	28440	28539	28467
62004	28605	211	0	1	1	0	1	0	0	0	0	0	4	0	4835	28284	0	0	0	23471	1000	1000	1000	5000	4	0	0	16082	28115	28518	3	10	1000	2000	1000	28631	28519	1	1	61001	1000	1000	0	1001	3	2	1002	4	1	2	1001	2	1	3	1	0	13562	9927	7104	3346	0	52	19749	3308	3832	11	49	44	27946	15151	12652	14421	1000	1000	28611	28739	28773	28723	28236

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.4h, v1.4h }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60205	120051	899	0	0	0	1	0	1	0	0	0	1	0	0	0	0	0	120020	119496	109461	55	60103	40100	10001	10000	30251	10000	10000	1079368	5736374	6119172	1	120036	0	120057	120051	111896	3	112417	50100	30200	20000	10000	60200	10000	10000	120035	120035	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	0	10000	0	0	0	10000	1	0	0	0	0	0	0	3210	2	108	1	1	119646	40000	10	0	9	10000	10000	40100	120036	120052	120052	120036	120052
60204	120051	899	0	0	0	0	0	0	1	0	0	1	0	1	0	0	0	120036	119503	109443	25	60100	40100	10000	10000	30100	10000	10000	1079126	5736084	6118285	1	120034	0	120051	120051	111881	3	112417	50100	30200	20000	10000	60200	10000	10000	120035	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	10000	1	0	0	0	0	0	0	3210	1	108	1	1	119656	40002	0	10	9	10000	10000	40100	120036	120052	120052	120052	120052
60204	120051	899	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	120036	119495	109459	25	60103	40100	10001	10000	30100	10000	10000	1079126	5736084	6118285	0	120027	0	120051	120051	111973	3	112417	50100	30200	20000	10000	60200	10000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	3210	1	108	1	1	119656	40002	10	10	0	10000	10000	40100	120036	120036	120036	120052	120036
60204	120051	900	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	120036	119495	109459	25	60100	40102	10000	10000	30100	10000	10000	1079552	5735293	6118285	1	120027	0	120051	120035	111896	3	112374	50100	30200	20000	10000	60200	10000	10000	120035	120051	1	1	50202	100	99	100	40100	10000	10000	0	100	10001	2	1	10001	0	0	1	10000	1	1	0	1	0	0	0	3210	1	100	1	1	119651	40004	0	10	9	10000	10000	40100	120042	120042	120058	120042	120042
60204	120041	899	1	0	1	0	1	0	0	0	0	2	0	1	0	0	1	120042	119512	109464	25	60106	40104	10002	10000	30100	10000	10000	1079423	5736374	6119172	0	120034	0	120057	120057	111897	3	112410	50100	30200	20000	10000	60200	10000	10000	120041	120057	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10002	0	0	1	10000	1	1	1	1	2	0	0	3210	1	121	1	1	119651	40004	10	0	9	10000	10000	40100	120058	120058	120042	120058	120042
60204	120057	900	1	0	1	0	1	0	0	0	0	2	0	1	0	0	1	120026	119530	109464	25	60106	40104	10002	10000	30100	10000	10000	1079423	5735593	6117518	0	120033	0	120041	120057	111897	3	112410	50100	30200	20000	10000	60200	10000	10000	120057	120041	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	2	1	10003	0	0	1	10000	1	1	1	1	1	0	0	3210	1	100	1	1	119669	40004	10	10	0	10000	10000	40100	120058	120058	120058	120042	120058
60204	120057	899	1	0	0	0	0	0	0	0	0	7	0	1	0	0	0	120026	119624	109449	25	60103	40104	10001	10000	30100	10000	10000	1079368	5736374	6117518	0	120033	0	120041	120057	111897	3	112415	50100	30200	20000	10000	60200	10000	10000	120057	120057	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	1	0	10001	0	1	1	10000	1	1	1	1	1	0	0	3210	1	121	1	1	119651	40002	0	10	9	10000	10000	40100	120058	120042	120058	120058	120058
60204	120057	899	1	0	0	0	1	0	0	0	0	2	0	0	0	0	1	120026	119512	109449	25	60106	40104	10002	10000	30100	10000	10000	1079423	5736374	6119172	1	120033	0	120041	120057	111897	3	112410	50100	30200	20000	10000	60200	10000	10000	120057	120057	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	2	0	10001	0	1	1	10000	0	1	1	1	0	0	0	3210	1	100	1	2	119669	40002	10	10	0	10000	10000	40100	120058	120046	120058	120042	120058
60204	120057	899	1	0	1	0	1	1	0	0	0	1	0	1	0	0	1	120042	119512	109464	25	60106	40104	10002	10000	30100	10000	10000	1079432	5736374	6119172	1	120038	0	120057	120057	111903	3	112410	50100	30200	20000	10000	60200	10000	10000	120060	120057	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10002	0	0	1	10000	0	1	1	1	0	0	0	3210	1	100	1	1	119651	40004	0	10	0	10000	10000	40100	120058	120042	120042	120042	120058
60204	120057	899	1	0	0	0	1	1	1	0	0	1	0	0	0	0	1	120042	119512	109464	25	60106	40104	10002	10000	30100	10000	10000	1079423	5736374	6121504	1	120035	0	120057	120057	111951	3	112516	53508	32305	20212	10000	60528	10000	10000	120041	120041	1	1	50201	100	99	100	40100	10000	10000	1	100	10002	2	0	10001	0	3	1	10000	1	1	1	1	0	0	0	3210	2	121	1	1	119651	40002	0	0	9	10000	10000	40100	120058	120058	120373	120780	120517

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0060

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120053	899	1	1	0	0	0	0	7	0	0	1	120026	119486	109461	25	60013	40012	10002	10000	30010	10000	10000	1079887	5735593	6125852	1	120029	0	120053	120053	111909	3	112438	50010	30020	20000	10000	60020	10000	10000	120053	120053	1	1	50021	10	9	10	40010	10000	10000	1	10	10001	1	1	10003	0	0	9	10000	1	1	1	1	0	0	3140	4	99	3	3	119671	40004	6	0	5	10000	10000	40010	120042	120057	120057	120042	120054
60024	120073	900	0	0	0	0	0	0	0	1	0	0	120043	119489	109449	25	60016	40014	10001	10000	30010	10000	10000	1079878	5736182	6125852	1	120032	3	120053	120041	111913	3	112438	50010	30020	20000	10000	60020	10000	10000	120053	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	2	1	10000	0	0	126	10000	0	0	1	0	0	0	3140	3	99	3	3	119665	40000	6	6	0	10000	10000	40010	120036	120036	120036	120036	120051
60024	120063	900	0	0	0	0	0	0	1	0	0	0	120032	119480	109455	25	60010	40012	10002	10000	30010	10000	10000	1079870	5735593	6125852	0	120029	0	120041	120053	111909	3	112450	50010	30020	20000	10000	60020	10000	10000	120041	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	1	0	14273	10000	1	0	1	0	0	0	3140	3	94	3	3	119650	40000	0	0	5	10000	10000	40010	120036	120048	120036	120048	120036
60024	120049	899	0	0	0	0	0	0	16	0	0	0	120032	119483	109458	25	60013	40010	10002	10000	30010	10000	10000	1079870	5735593	6123500	0	120029	0	120053	120041	111909	3	112450	50010	30020	20000	10000	60020	10000	10000	120041	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	114	10000	1	0	0	0	0	0	3140	3	99	3	3	119674	40004	9	6	5	10000	10000	40010	120054	120054	120057	120057	120057
60024	120064	899	1	1	0	0	0	0	2	0	0	0	120041	119486	109461	25	60016	40012	10001	10000	30010	10000	10000	1079878	5736182	6123500	0	120076	0	120053	120053	111924	3	112438	50010	30020	20000	10000	60020	10000	10000	120053	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	171	10000	1	0	1	0	0	0	3140	3	99	3	3	119665	40002	0	6	0	10000	10000	40010	120036	120051	120048	120036	120048
60024	120061	899	0	0	0	0	0	1	1	0	0	0	120020	119489	109455	25	60013	40012	10000	10000	30010	10000	10000	1079870	5736326	6125852	1	120017	0	120053	120056	111909	3	112453	50010	30020	20000	10000	60020	10000	10000	120053	120053	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	0	10000	1	0	6	10000	0	0	0	0	0	0	3140	3	99	3	3	119665	40002	6	0	5	10000	10000	40010	120048	120048	120036	120048	120036
60024	120068	899	0	0	0	0	0	0	25	0	0	1	120038	119486	109461	25	60016	40014	10002	10000	30010	10000	10000	1079977	5736182	6125852	1	120029	0	120053	120041	111921	3	112450	50010	30020	20000	10000	60020	10000	10000	120054	120054	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10008	1	0	27	10000	1	0	0	0	0	0	3140	3	94	3	3	119665	40002	0	6	0	10000	10000	40010	120051	120036	120036	120036	120036
60024	120050	899	0	0	0	0	1	0	12	1	0	0	120020	119493	109455	25	60013	40012	10002	10000	30010	10000	10000	1079878	5735593	6125852	1	120029	0	120041	120056	111921	3	112499	50010	30020	20000	10000	60020	10000	10000	120053	120041	2	1	50021	10	9	10	40010	10000	10000	1	10	10039	4	1	10000	1	0	150	10000	1	0	1	0	0	0	3140	3	99	3	3	119668	40002	6	6	5	10000	10000	40010	120048	120048	120036	120036	120036
60024	120053	899	0	0	0	0	0	0	1	1	0	0	120020	119483	109458	25	60013	40012	10001	10000	30010	10000	10000	1079878	5736182	6125852	1	120017	0	120053	120041	111924	3	112453	50010	30020	20128	10000	60020	10000	10000	120047	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	1	0	15	10000	1	0	1	0	0	0	3140	3	94	3	3	119665	40002	9	6	5	10000	10000	40010	120048	120036	120048	120048	120048
60024	120048	899	0	0	0	0	0	0	0	1	0	0	120032	119497	109455	25	60010	40012	10000	10000	30010	10000	10000	1079906	5736326	6125852	1	120082	0	120053	120054	111924	3	112455	50278	30020	20000	10000	60020	10000	10000	120052	120047	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	21	10000	1	0	0	0	0	0	3140	3	99	3	3	119650	40002	0	6	5	10000	10000	40010	120036	120036	120036	120036	120048

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.4h, v1.4h }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60205	120051	899	0	0	0	0	0	1	1	0	0	6	0	0	0	120085	119503	109459	25	60103	40100	10001	10000	30100	10000	10000	1079552	5736084	6118285	0	120027	0	120035	120054	111900	0	3	112417	50100	30200	20000	10000	60200	10000	10000	120035	120035	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	0	10000	0	9	10000	1	1	0	0	0	3210	2	121	2	2	119666	40002	13	10	12	10000	10000	40100	120052	120036	120055	120036	120052
60204	120035	899	0	0	0	0	0	0	0	0	0	1	0	0	0	120039	119503	109461	25	60103	40102	10001	10000	30100	10000	10000	1079396	5736230	6118285	1	120027	0	120051	120035	111900	0	3	112407	50100	30200	20000	10000	60200	10000	10000	120035	120051	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	10000	0	0	0	0	0	3210	2	135	2	2	119666	40000	10	0	12	10000	10000	40100	120052	120055	120055	120055	120088
60204	120054	899	0	0	0	0	0	1	0	0	0	1	0	0	0	120039	119503	109461	25	60100	40102	10001	10000	30100	10000	10000	1079126	5736084	6118285	1	120030	0	120054	120054	111896	0	3	112407	50100	30200	20000	10000	60200	10000	10065	120054	120054	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	1	1	0	0	0	3210	2	108	2	2	119666	40002	10	0	12	10000	10000	40100	120055	120036	120055	120055	120055
60204	120054	899	0	0	0	0	0	1	1	0	0	1	0	0	0	120020	119512	109443	25	60103	40100	10000	10000	30100	10000	10000	1079552	5735293	6119016	1	120011	0	120054	120054	111900	0	3	112374	50100	30200	20000	10000	60200	10000	10000	120035	120035	2	1	50201	100	99	100	40100	10000	10000	1	100	10001	0	1	10000	0	0	10000	1	0	0	0	0	3210	2	135	2	2	119646	40002	13	0	12	10000	10000	40100	120040	120055	120055	120055	120055
60204	120054	899	0	0	0	0	0	0	0	0	0	1	0	1	0	120039	119503	109443	25	60100	40102	10001	10000	30100	10000	10000	1079396	5736230	6117599	1	120030	0	120054	120051	111896	0	3	112407	50365	30200	20000	10000	60200	10000	10000	120054	120051	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10002	0	0	10000	1	0	0	0	0	3210	2	135	2	2	119646	40002	13	0	0	10000	10000	40100	120059	120061	120036	120036	120055
60204	120035	899	0	0	0	0	0	0	0	0	0	1	0	0	0	120020	119509	109461	25	60103	40102	10001	10000	30100	10000	10000	1079552	5736084	6118285	1	120030	0	120054	120054	111900	0	3	112374	50100	30200	20000	10000	60200	10000	10000	120035	120051	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	0	10000	0	0	10001	1	0	0	0	0	3210	2	108	2	2	119656	40000	0	0	12	10000	10000	40100	120036	120055	120052	120036	120055
60204	120035	899	0	0	0	0	0	0	0	0	0	0	0	0	0	120020	119503	109459	25	60103	40100	10001	10000	30100	10000	10000	1079552	5736230	6117599	1	120011	0	120054	120035	111881	0	3	112407	50100	30200	20000	10000	60200	10000	10000	120035	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	1	0	0	0	0	3210	2	135	2	2	119646	40000	10	13	0	10000	10000	40100	120052	120052	120052	120055	120036
60204	120051	899	0	0	0	0	0	0	0	0	0	1	0	1	0	120039	119503	109461	25	60103	40100	10001	10000	30100	10000	10000	1079396	5736230	6119016	1	120030	3	120051	120051	111896	0	3	112417	50100	30200	20000	10000	60200	10000	10000	120036	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	1	1	0	0	0	3210	2	108	2	2	119656	40002	0	0	9	10000	10000	40100	120052	120055	120052	120052	120055
60204	120054	899	0	0	0	0	0	0	0	0	0	1	0	0	0	120020	119514	109443	25	60103	40102	10001	10000	30100	10000	10000	1079126	5736326	6119016	0	120030	0	120051	120091	111900	0	3	112417	50100	30200	20000	10000	60200	10000	10000	120055	120051	3	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	165	10000	1	0	0	0	0	3210	2	121	2	2	119646	40000	13	13	12	10000	10000	40100	120628	120036	120334	120159	120052
60204	120035	899	0	0	0	0	0	1	0	0	0	1	0	1	0	120039	119509	109443	25	60106	40102	10002	10000	30100	10000	10000	1079126	5736230	6118285	0	120030	0	120054	120054	111900	0	3	112407	50100	30200	20000	10000	60200	10000	10000	120035	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	3	10000	1	1	0	0	0	3210	2	135	2	2	119666	40015	13	13	12	10000	10000	40100	120052	120036	120056	120058	120055

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0057

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120052	899	0	0	1	0	0	0	2	1	0	1	120045	119484	109468	25	60016	40014	10001	10000	30010	10000	10000	1079858	5736084	6125746	1	120030	120054	120054	111922	3	112457	50010	30020	20000	10000	60020	10000	10000	120066	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	15	10000	1	1	1	1	0	0	3140	14	99	5	7	119678	40004	13	10	12	10000	10000	40010	120061	120061	120058	120061	120042
60024	120060	900	1	0	0	1	0	0	2	0	0	0	120045	119493	109467	25	60016	40014	10002	10000	30010	10000	10000	1079870	5736374	6123500	1	120036	120060	120057	111928	3	112457	50010	30020	20000	10000	60020	10000	10000	120439	120088	1	1	50021	10	9	10	40010	10000	10000	1	10	10002	1	0	10001	0	1	1	10000	1	1	1	1	0	0	3140	8	99	7	5	119675	40004	13	10	12	10000	10000	40010	120061	120111	120058	120061	120059
60024	120057	899	1	1	0	1	0	0	2	0	0	2	120046	119493	109449	25	60013	40012	10002	10000	30010	10000	10000	1079942	5736518	6126051	1	120036	120060	120060	111933	3	112457	50010	30020	20000	10000	60020	10000	10000	120063	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	1	10001	0	0	1	10000	1	1	1	1	0	0	3140	9	99	7	5	119678	40004	10	13	9	10000	10000	40010	120061	120061	120117	120089	120055
60024	120051	900	0	0	0	0	0	0	0	0	0	0	120036	119487	109459	25	60010	40012	10001	10000	30010	10000	10000	1079888	5736230	6125746	1	120030	120054	120035	111922	3	112451	50010	30020	20126	10000	60020	10000	10000	120055	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	0	3140	11	99	5	7	119680	40004	10	13	12	10000	10000	40010	120061	120058	120058	120061	120061
60024	120060	899	1	0	0	0	0	0	1	1	0	0	120045	119490	109464	25	60016	40014	10002	10000	30010	10000	10000	1079942	5735593	6126051	0	120036	120061	120060	111928	3	112454	50010	30020	20000	10000	60020	10000	10000	120060	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10001	9	1	1	10000	1	1	1	1	0	0	3140	9	99	5	7	119675	40004	13	13	12	10000	10000	40010	120061	120061	120061	120042	120061
60024	120041	899	1	1	0	1	0	0	2	1	0	0	120042	119493	109467	25	60016	40014	10002	10000	30010	10000	10000	1079942	5735593	6126051	1	120036	120041	120060	111928	3	112457	50010	30020	20000	10000	60020	10000	10000	120058	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	3	1	10002	0	1	1	10000	1	1	1	1	0	0	3140	9	99	7	5	119678	40004	10	10	12	10000	10000	40010	120061	120042	120061	120061	120061
60024	120060	899	1	0	0	1	0	0	2	0	0	0	120026	119493	109464	25	60016	40014	10002	10000	30010	10000	10000	1079942	5736518	6123500	1	120036	120060	120057	111928	3	112454	50010	30020	20000	10000	60020	10000	10000	120451	120073	1	1	50022	10	9	10	40010	10000	10000	0	10	10001	3	1	10002	0	0	1	10000	1	1	1	1	0	0	3140	11	99	5	7	119678	40002	13	10	12	10000	10000	40010	120061	120061	120061	120061	120058
60024	120060	899	1	1	0	0	0	0	2	0	0	0	120045	119493	109467	25	60016	40014	10002	10000	30010	10000	10000	1079942	5735593	6126051	1	120036	120060	120041	111928	3	112457	50010	30020	20000	10000	60020	10000	10000	120063	120110	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	2	0	10001	0	1	1	10000	0	1	1	1	2	0	3140	10	99	5	7	119678	40002	13	13	9	10000	10000	40010	120061	120061	120061	120061	120058
60024	120060	899	1	1	0	1	0	0	2	0	0	0	120026	119493	109464	25	60016	40014	10002	10000	30010	10000	10000	1079870	5735593	6123500	1	120033	120057	120057	111909	3	112454	50010	30020	20000	10000	60020	10000	10000	120071	120100	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	3140	9	99	6	7	119669	40002	10	13	0	10000	10000	40010	120052	120052	120055	120055	120052
60024	120051	900	0	0	0	0	0	0	1	0	0	0	120039	119487	109443	25	60013	40010	10001	10000	30010	10000	10000	1079858	5736084	6125879	1	120030	120054	120054	111922	3	112451	50010	30020	20000	10000	60394	10000	10000	120065	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	174	10000	1	0	1	0	0	0	3140	9	99	5	8	119682	40004	10	13	9	10000	10000	40010	120042	120061	120058	120061	120058

Test 4: throughput

Count: 8

Code:

  ld1 { v0.4h, v1.4h }, [x6]
  ld1 { v0.4h, v1.4h }, [x6]
  ld1 { v0.4h, v1.4h }, [x6]
  ld1 { v0.4h, v1.4h }, [x6]
  ld1 { v0.4h, v1.4h }, [x6]
  ld1 { v0.4h, v1.4h }, [x6]
  ld1 { v0.4h, v1.4h }, [x6]
  ld1 { v0.4h, v1.4h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160205	26728	200	0	0	0	0	0	0	44	0	0	1	26716	2	1	1	16	25	80100	100	80000	100	80000	500	1172377	1	26682	26731	26727	6630	3	6689	80100	200	160000	200	80000	26731	26707	1	1	80201	100	99	100	100	80000	80000	1	100	80000	43	80039	0	30	38	80000	6	0	0	0	0	5110	1	16	1	1	26728	14	10	0	80000	80000	100	26708	26732	26732	26728	26833
160204	26732	200	0	0	0	1	0	0	44	0	0	0	26716	0	12	1	19	25	80100	100	80000	100	80000	500	1168880	1	26702	26731	26727	6650	3	6685	80100	200	160000	200	80000	26731	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80000	0	32	42	80000	0	1	0	43	0	5110	1	16	1	1	26728	14	10	0	80000	80000	100	26735	26732	26733	26708	26844
160204	26736	200	0	0	0	0	0	0	44	1	0	0	26716	0	0	0	19	25	80100	100	80000	100	80000	500	1187796	1	26682	26731	26731	6654	3	6665	80100	200	160000	200	80000	26731	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80039	0	17	44	80038	0	0	39	0	0	5110	1	16	1	1	26728	14	14	4	80000	80000	100	26708	26708	26708	26708	26842
160204	26717	200	0	0	1	0	0	0	44	0	0	1	26692	2	1	0	16	25	80100	100	80000	100	80000	500	1168880	1	26702	26707	26707	6654	3	6665	80100	200	160000	200	80000	26707	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	80039	0	25	44	80038	6	0	38	0	0	5110	1	16	1	1	26728	14	0	0	80000	80000	100	26732	26732	26708	26708	26922
160204	26958	200	0	0	0	0	0	0	44	0	0	1	26716	2	1	1	0	25	80100	100	80000	100	80000	500	1166807	1	26702	26727	26707	6654	3	6689	80100	200	160000	200	80000	26731	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	44	80039	0	29	42	80038	6	1	38	44	0	5110	1	16	1	1	26728	0	14	7	80000	80000	100	26732	26732	26708	26732	26815
160204	26736	200	0	0	0	0	0	0	0	0	0	0	26716	2	0	0	19	25	80100	100	80000	100	80000	500	1169085	1	26706	26727	26707	6654	3	6689	80100	200	160000	200	80000	26731	26727	2	1	80201	100	99	100	100	80000	80000	0	100	80000	43	80039	0	29	41	80039	6	1	38	44	0	5110	1	16	1	1	26728	14	14	7	80000	80000	100	26732	26708	26732	26732	26732
160204	26738	200	1	0	0	0	0	0	45	0	0	1	26722	0	1	0	19	25	80100	100	80000	100	80000	500	1168880	1	26682	26707	26731	6654	3	6689	80100	200	160000	200	80000	26731	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	80039	0	36	41	80000	6	1	0	44	0	5110	1	16	1	1	26728	0	0	0	80000	80000	100	26708	26728	26733	26732	26846
160204	26736	200	1	0	1	1	0	0	0	0	0	0	26716	0	0	0	19	25	80100	100	80000	100	80000	500	1180956	1	26682	26731	26731	6630	3	6665	80100	200	160000	200	80000	26731	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	80000	0	31	3	80038	0	0	39	44	0	5110	1	16	1	1	26728	14	0	0	80000	80000	100	26732	26708	26732	26732	26818
160204	26717	200	0	0	0	0	0	0	44	0	0	1	26712	2	0	1	19	25	80100	100	80000	100	80000	500	1168880	1	26706	26731	26731	6630	3	6689	80100	200	160000	200	80000	26707	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	80039	0	30	38	80000	6	0	39	0	0	5110	1	16	1	1	26724	10	0	0	80000	80000	100	26732	26732	26732	26708	26745
160204	26727	200	1	0	1	0	0	0	44	1	0	0	26716	2	1	1	0	25	80100	100	80000	100	80000	500	1176351	1	26702	26707	26731	6654	3	6689	80100	200	160000	200	80000	26731	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80039	0	0	224	80039	6	1	39	44	0	5110	1	16	1	1	26704	14	14	7	80000	80000	100	26732	26728	26728	26728	26738

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	18	1e	1f	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160025	26734	200	1	1	0	45	0	1	0	0	26692	0	0	18	12	25	80010	10	80000	10	80000	50	1175306	1	5	26702	26727	26722	6668	0	3	6707	80010	20	160000	20	80000	26722	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	39	0	80035	0	0	156	80039	6	1	35	43	0	5020	0	0	20	16	12	11	26719	10	0	4	80000	80000	10	26728	26728	26708	26708	26723
160024	26882	200	1	0	0	45	0	0	0	2	26712	2	18	0	0	25	80010	10	80000	10	80000	50	1170107	0	0	26715	26707	26722	6653	0	3	6690	80010	20	160000	20	80000	26722	26722	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	0	80035	34	0	39	80039	6	1	35	43	0	5020	5	3	11	16	10	10	26724	6	10	2	80000	80000	10	26708	26708	26728	26728	26708
160024	26850	200	0	0	0	41	0	0	0	2	26712	0	0	12	0	25	80010	10	80000	10	80000	50	1169324	0	0	26682	26707	26727	6668	0	3	6707	80010	20	160000	20	80000	26727	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	39	0	80035	8	0	9	80039	6	1	0	0	0	5020	0	0	5	16	7	12	26724	10	10	4	80000	80000	10	26708	26728	26728	26728	26766
160024	26722	200	0	0	0	46	0	1	0	1	26692	2	12	12	16	25	80010	10	80000	10	80000	50	1168880	0	0	26684	26727	26727	6653	0	3	6707	80010	20	160000	20	80000	26727	26707	1	1	80021	10	9	10	10	80000	80000	0	10	80000	39	0	80035	32	0	3	80039	6	1	0	43	0	5020	0	0	8	16	8	8	26719	6	6	4	80000	80000	10	26728	26728	26708	26708	26843
160024	26717	200	0	0	0	0	0	0	0	2	26707	2	12	18	16	25	80010	10	80000	10	80000	50	1168746	0	0	26682	26727	26707	6673	0	3	6707	80010	20	160000	20	80000	26727	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	39	0	80035	32	0	3378	80039	6	0	35	0	0	5020	0	0	8	25	7	10	26724	0	10	2	80000	80000	10	26728	26708	26708	26728	26723
160024	26889	201	0	0	0	45	0	1	0	1	26905	2	18	12	16	25	80010	10	80000	10	80000	50	1169178	0	0	26697	26727	26707	6653	0	3	6707	80010	20	160000	20	80000	26727	26707	1	1	80021	10	9	10	10	80000	80000	0	10	80000	39	0	80035	31	0	35	80000	6	1	35	43	0	5020	0	0	6	16	8	6	26724	6	6	2	80000	80000	10	26728	26728	26728	26708	26851
160024	26731	200	0	0	0	41	0	0	0	2	26692	0	12	12	0	25	80010	10	80000	10	80000	50	1173183	0	0	26682	26722	26707	6668	0	3	6707	80010	20	160000	20	80000	26727	26707	1	1	80021	10	9	10	10	80000	80000	0	10	80000	39	0	80000	2	0	0	80039	6	1	39	43	0	5020	0	0	7	16	4	7	26724	0	10	4	80000	80000	10	26728	26728	26728	26708	26814
160024	26729	200	0	0	0	0	0	0	0	2	26712	2	12	12	0	25	80010	10	80000	10	80000	50	1168880	0	0	26702	26727	26727	6653	0	3	6707	80010	20	160000	20	80000	26727	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	39	0	80035	29	0	42	80035	6	1	35	0	0	5020	0	0	6	16	9	5	26704	6	6	4	80000	80000	10	26708	26708	26708	26708	26733
160024	26733	200	1	1	0	45	0	1	0	0	26712	2	0	0	11	25	80010	10	80000	10	80000	50	1168880	1	0	26697	26707	26707	6672	0	3	6707	80010	20	160000	20	80000	26707	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	39	0	80036	28	0	42	80000	6	1	35	43	0	5020	0	0	8	16	7	10	26704	0	0	4	80000	80000	10	26728	26728	26708	26728	26826
160024	26716	200	1	0	0	0	0	1	0	2	26712	2	0	0	0	25	80010	10	80000	10	80000	50	1174628	0	0	26697	26707	26727	6672	0	3	6707	80010	20	160000	20	80000	26707	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	39	0	80035	29	0	3412	80039	6	1	0	43	0	5020	0	0	8	16	8	9	26724	10	10	4	80000	80000	10	26728	26708	26723	26728	26723

LD1 (multiple, 2 regs, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations